diff options
| author | Julius Werner <jwerner@chromium.org> | 2016-03-23 16:08:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-04-05 13:35:09 +0200 |
| commit | c71359413dfbf7940603f23f1f52a790d50e75dc (patch) | |
| tree | 873dba6fdb0f793579f77d30c6950c3b167caaf5 /src/soc/mediatek | |
| parent | 7b9bca0b2b1830262daffd16f285e868d241391b (diff) | |
| download | coreboot-c71359413dfbf7940603f23f1f52a790d50e75dc.tar.xz | |
google/oak: Log hardware watchdog in eventlog
The MT8173 hardware watchdog can assert an external signal which we use
to reset the TPM on Oak. Therefore we do not need to do the same
double-reset dance as on other Chromebooks to ensure that we reset in a
correct state.
Still, we have a situation where we need to reconfigure the watchdog
early in the bootblock in a way that will clear information about the
previous reboot from the status register, and we need that information
later in ramstage to log the right event. Let's reuse the same watchdog
tombstone mechanism from other boards, except that we don't perform a
second reset and the tombstone is simply used to communicate between
bootblock and ramstage within the same boot.
BRANCH=None
BUG=None
TEST=Run 'mem w 0x10007004 0x8' on Oak, observe how it reboots and how
'mosys eventlog list' shows a hardware watchdog reboot event afterwards.
Change-Id: I1ade018eba652af91814fdaec233b9920f2df01f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07af37e11499e86e730f7581862e8f0d67a04218
Original-Change-Id: I0b9c6b83b20d6e1362d650ac2ee49fff45b29767
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/334449
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14234
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/memlayout.ld | 3 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/wdt.c | 6 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 771f32652e..5b92153142 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -40,7 +40,8 @@ SECTIONS SRAM_START(0x00100000) VBOOT2_WORK(0x00100000, 12K) PRERAM_CBMEM_CONSOLE(0x00103000, 16K) - PRERAM_CBFS_CACHE(0x00107000, 16K) + WATCHDOG_TOMBSTONE(0x00107000, 4) + PRERAM_CBFS_CACHE(0x00107004, 16K - 4) TIMESTAMP(0x0010B000, 4K) ROMSTAGE(0x0010C000, 92K) STACK(0x00124000, 16K) diff --git a/src/soc/mediatek/mt8173/wdt.c b/src/soc/mediatek/mt8173/wdt.c index ba63c13b6d..93ffe09209 100644 --- a/src/soc/mediatek/mt8173/wdt.c +++ b/src/soc/mediatek/mt8173/wdt.c @@ -18,6 +18,7 @@ #include <reset.h> #include <soc/addressmap.h> #include <soc/wdt.h> +#include <vendorcode/google/chromeos/chromeos.h> static struct mt8173_wdt_regs * const mt8173_wdt = (void *)RGU_BASE; @@ -29,9 +30,10 @@ int mtk_wdt_init(void) wdt_sta = read32(&mt8173_wdt->wdt_status); printk(BIOS_INFO, "WDT: Last reset was "); - if (wdt_sta & MTK_WDT_STA_HW_RST) + if (wdt_sta & MTK_WDT_STA_HW_RST) { printk(BIOS_INFO, "hardware watchdog\n"); - else if (wdt_sta & MTK_WDT_STA_SW_RST) + mark_watchdog_tombstone(); + } else if (wdt_sta & MTK_WDT_STA_SW_RST) printk(BIOS_INFO, "normal software reboot\n"); else if (wdt_sta & MTK_WDT_STA_SPM_RST) printk(BIOS_INFO, "SPM reboot\n"); |