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authorTristan Shieh <tristan.shieh@mediatek.com>2018-06-01 14:33:11 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-06-21 09:40:06 +0000
commit4c6dfbc2c10a14fb816c681fb03b601412ea7c3b (patch)
tree496dae29a18d61da7e16abf692fc7b79840d3d85 /src/soc/mediatek
parent53dabc29f2eb44761f4bc28e7f5e211bfeffb234 (diff)
downloadcoreboot-4c6dfbc2c10a14fb816c681fb03b601412ea7c3b.tar.xz
mediatek/mt8183: Add watchdog timer support
Using common watchdog timer (WDT) code for reset. Set up watchdog timer in mtk_wdt_init() to get reset status and disable auto-reboot. Link common do_hard_reset() to support hard reset. BUG=b:80501386 BRANCH=none TEST=both mtk_wdt_init() and do_hard_reset() work on Kukui. Change-Id: I4be3a133dbb8a64604133cefb0c5f02d01afd0d4 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27026 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek')
-rw-r--r--src/soc/mediatek/mt8183/Makefile.inc5
-rw-r--r--src/soc/mediatek/mt8183/bootblock.c22
-rw-r--r--src/soc/mediatek/mt8183/include/soc/addressmap.h1
3 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index 9f80500c0e..954ab216c3 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -1,27 +1,32 @@
ifeq ($(CONFIG_SOC_MEDIATEK_MT8183),y)
+bootblock-y += bootblock.c
bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
bootblock-$(CONFIG_SPI_FLASH) += spi.c
bootblock-y += ../common/timer.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
endif
+bootblock-y += ../common/wdt.c
verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
verstage-$(CONFIG_SPI_FLASH) += spi.c
verstage-y += ../common/timer.c
verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
+verstage-y += ../common/wdt.c
romstage-$(CONFIG_SPI_FLASH) += flash_controller.c
romstage-$(CONFIG_SPI_FLASH) += spi.c
romstage-y += ../common/timer.c
romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
+romstage-y += ../common/wdt.c
ramstage-y += ../common/cbmem.c emi.c
ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
ramstage-y += ../common/timer.c
ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
+ramstage-y += ../common/wdt.c
CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include
CPPFLAGS_common += -Isrc/soc/mediatek/common/include
diff --git a/src/soc/mediatek/mt8183/bootblock.c b/src/soc/mediatek/mt8183/bootblock.c
new file mode 100644
index 0000000000..4eca0f145c
--- /dev/null
+++ b/src/soc/mediatek/mt8183/bootblock.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/wdt.h>
+
+void bootblock_soc_init(void)
+{
+ mtk_wdt_init();
+}
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index 59f4acf3f8..bbb40943a1 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -22,6 +22,7 @@ enum {
};
enum {
+ RGU_BASE = IO_PHYS + 0x00007000,
GPT_BASE = IO_PHYS + 0x00008000,
UART0_BASE = IO_PHYS + 0x01002000,
};