diff options
author | Itamar <itamar.gold@mediatek.com> | 2015-07-31 17:10:46 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-22 19:31:06 +0100 |
commit | f585af395d3b88d7a415453e2f2d532797f3962c (patch) | |
tree | 35732372d51b0344d8e93a38f91c566e347b0d51 /src/soc/mediatek | |
parent | ab0df6d5a4c597db09a65043d1e5f9834cce4f9b (diff) | |
download | coreboot-f585af395d3b88d7a415453e2f2d532797f3962c.tar.xz |
mediatek/mt8173: add watchdog driver
[pg: split original commit into multiple commits]
Change-Id: I0dc8d9855c98c077d4a47227de0c504c3a846953
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13050
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/mediatek')
-rw-r--r-- | src/soc/mediatek/mt8173/Kconfig | 1 | ||||
-rw-r--r-- | src/soc/mediatek/mt8173/Makefile.inc | 2 | ||||
-rw-r--r-- | src/soc/mediatek/mt8173/bootblock.c | 4 | ||||
-rw-r--r-- | src/soc/mediatek/mt8173/include/soc/wdt.h | 54 | ||||
-rw-r--r-- | src/soc/mediatek/mt8173/wdt.c | 64 |
5 files changed, 125 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 5158651090..d8f1116261 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -13,6 +13,7 @@ config SOC_MEDIATEK_MT8173 select GENERIC_UDELAY select HAS_PRECBMEM_TIMESTAMP_REGION select GENERIC_GPIO_LIB + select HAVE_HARD_RESET if SOC_MEDIATEK_MT8173 diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index eec1cac61b..5ca882f0c3 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -26,6 +26,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c +bootblock-y += wdt.c ################################################################################ @@ -46,6 +47,7 @@ ramstage-y += soc.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += gpio.c +ramstage-y += wdt.c ################################################################################ diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index 9b064707ec..0b6d1ea979 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -16,6 +16,7 @@ #include <bootblock_common.h> #include <soc/mt6391.h> #include <soc/pll.h> +#include <soc/wdt.h> void bootblock_soc_init(void) { @@ -26,4 +27,7 @@ void bootblock_soc_init(void) /* post init pll */ mt_pll_post_init(); + + /* init watch dog, will disable AP watch dog */ + mtk_wdt_init(); } diff --git a/src/soc/mediatek/mt8173/include/soc/wdt.h b/src/soc/mediatek/mt8173/include/soc/wdt.h new file mode 100644 index 0000000000..f4df1e12d7 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/wdt.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8173_WDT_H +#define SOC_MEDIATEK_MT8173_WDT_H + +#include <stdint.h> + +struct mt8173_wdt_regs { + u32 wdt_mode; + u32 wdt_length; + u32 wdt_restart; + u32 wdt_status; + u32 wdt_interval; + u32 wdt_swrst; + u32 wdt_swsysrst; + u32 reserved[9]; + u32 wdt_debug_ctrl; +}; + +/* WDT_MODE */ +enum { + MTK_WDT_MODE_KEY = 0x22000000, + MTK_WDT_MODE_DUAL_MODE = 1 << 6, + MTK_WDT_MODE_IRQ = 1 << 3, + MTK_WDT_MODE_EXTEN = 1 << 2, + MTK_WDT_MODE_EXT_POL = 1 << 1, + MTK_WDT_MODE_ENABLE = 1 << 0 +}; + +/* WDT_RESET */ +enum { + MTK_WDT_SWRST_KEY = 0x1209, + MTK_WDT_STA_SPM_RST = 1 << 1, + MTK_WDT_STA_SW_RST = 1 << 30, + MTK_WDT_STA_HW_RST = 1 << 31 +}; + +int mtk_wdt_init(void); + +#endif /* SOC_MEDIATEK_MT8173_WDT_H */ + diff --git a/src/soc/mediatek/mt8173/wdt.c b/src/soc/mediatek/mt8173/wdt.c new file mode 100644 index 0000000000..ba63c13b6d --- /dev/null +++ b/src/soc/mediatek/mt8173/wdt.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <reset.h> +#include <soc/addressmap.h> +#include <soc/wdt.h> + +static struct mt8173_wdt_regs * const mt8173_wdt = (void *)RGU_BASE; + +int mtk_wdt_init(void) +{ + uint32_t wdt_sta; + + /* Write Mode register will clear status register */ + wdt_sta = read32(&mt8173_wdt->wdt_status); + + printk(BIOS_INFO, "WDT: Last reset was "); + if (wdt_sta & MTK_WDT_STA_HW_RST) + printk(BIOS_INFO, "hardware watchdog\n"); + else if (wdt_sta & MTK_WDT_STA_SW_RST) + printk(BIOS_INFO, "normal software reboot\n"); + else if (wdt_sta & MTK_WDT_STA_SPM_RST) + printk(BIOS_INFO, "SPM reboot\n"); + else if (!wdt_sta) + printk(BIOS_INFO, "cold boot\n"); + else + printk(BIOS_INFO, "unexpected reset type: %#.8x\n", wdt_sta); + + /* Config watchdog reboot mode: + * Clearing bits: + * DUAL_MODE & IRQ: trigger reset instead of irq then reset. + * EXT_POL: select watchdog output signal as active low. + * ENABLE: disable watchdog on initialization. + * Setting bit EXTEN to enable watchdog output. + */ + clrsetbits_le32(&mt8173_wdt->wdt_mode, + MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ | + MTK_WDT_MODE_EXT_POL | MTK_WDT_MODE_ENABLE, + MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + + return wdt_sta; +} + +void hard_reset(void) +{ + write32(&mt8173_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); + + while (1) + ; +} |