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authorElyes HAOUAS <ehaouas@noos.fr>2019-12-19 07:47:52 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-12-20 17:49:29 +0000
commitba9b504ec5d8bc42f56cb085749c1296b1291ba9 (patch)
treee8a52663d7b6add1437fe474986e88e5f90d53d4 /src/soc/mediatek
parent361a935332489c635192b39204c7ec7af1667c8f (diff)
downloadcoreboot-ba9b504ec5d8bc42f56cb085749c1296b1291ba9.tar.xz
src: Replace min/max() with MIN/MAX()
Change-Id: I63b95144f2022685c60a1bd6de5af3c1f059992e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37828 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek')
-rw-r--r--src/soc/mediatek/common/cbmem.c4
-rw-r--r--src/soc/mediatek/mt8173/dramc_pi_calibration_api.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c
index 1a55d0113e..accafeb9c0 100644
--- a/src/soc/mediatek/common/cbmem.c
+++ b/src/soc/mediatek/common/cbmem.c
@@ -14,8 +14,8 @@
*/
#include <cbmem.h>
+#include <commonlib/helpers.h>
#include <stddef.h>
-#include <stdlib.h>
#include <symbols.h>
#include <soc/emi.h>
@@ -23,5 +23,5 @@
void *cbmem_top_chipset(void)
{
- return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS);
+ return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS);
}
diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
index a22d7e22d1..492238a80c 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
@@ -308,7 +308,7 @@ static u8 dqs_gw_fine_tune_calib(u32 channel, u8 fine_val)
int matches = 0, sum = 0;
/* fine tune range from 0 to 127 */
- fine_val = min(max(fine_val, 0 - delta[0]), 127 - delta[6]);
+ fine_val = MIN(MAX(fine_val, 0 - delta[0]), 127 - delta[6]);
/* test gw fine tune */
for (i = 0; i < ARRAY_SIZE(delta); i++) {
@@ -443,7 +443,7 @@ void dramc_rankinctl_config(u32 channel,
if (is_dual_rank(channel, sdram_params)) {
/* RANKINCTL_ROOT1 = DQSINCTL + reg_TX_DLY_DQSGATE */
- value = min(opt_gw_coarse_value[channel][0],
+ value = MIN(opt_gw_coarse_value[channel][0],
opt_gw_coarse_value[channel][1]) >> 2;
clrsetbits32(&ch[channel].ao_regs->dummy, 0xf, value);