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| author | Huayang Duan <huayang.duan@mediatek.com> | 2018-09-26 16:16:38 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-08 17:20:38 +0000 |
| commit | 6bb72e4ab9217d4071330eac512f7cba4728accf (patch) | |
| tree | 32306b5acb4cbcc75e30b05a477cd4a7f869fc16 /src/soc/mediatek | |
| parent | cede791d4f6381032056f54355c621b4e125fdba (diff) | |
| download | coreboot-6bb72e4ab9217d4071330eac512f7cba4728accf.tar.xz | |
mediatek/mt8183: Add DDR driver of write leveling part
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: Ibde5f613c61c36f5c9b405326fd18a3fd16cca56
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/28840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 3f4bd94639..823c512507 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -80,6 +80,25 @@ static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back); } +static void dramc_write_leveling(u8 chn, u8 rank, + const u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]) +{ + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], + SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK, 0); + + for (u8 i = 0; i < DQS_NUMBER; i++) { + s32 wrlevel_dq_delay = wr_level[chn][rank][i] + 0x10; + assert(wrlevel_dq_delay < 0x40); + + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[7], + FINE_TUNE_PBYTE_MASK | FINE_TUNE_DQM_MASK | + FINE_TUNE_DQ_MASK, + (wr_level[chn][rank][i] << FINE_TUNE_PBYTE_SHIFT) | + (wrlevel_dq_delay << FINE_TUNE_DQM_SHIFT) | + (wrlevel_dq_delay << FINE_TUNE_DQ_SHIFT)); + } +} + static void cmd_bus_training(u8 chn, u8 rank, const struct sdram_params *params) { @@ -275,6 +294,8 @@ void dramc_calibrate_all_channels(const struct sdram_params *pams) dramc_show("Start K ch:%d, rank:%d\n", chn, rk); auto_refresh_switch(chn, 0); cmd_bus_training(chn, rk, pams); + dramc_write_leveling(chn, rk, pams->wr_level); + auto_refresh_switch(chn, 1); } } } |