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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-05 10:36:45 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-08 09:46:16 +0000
commit88607a4b1002ed6acc7f316f274feea2fd861095 (patch)
treee004c85f36109da78872b88875d4f0ea1c30aaff /src/soc/mediatek
parentd9169f826a3c19a7380a7d73c7126e52eb62e77d (diff)
downloadcoreboot-88607a4b1002ed6acc7f316f274feea2fd861095.tar.xz
src: Use tabs for indentation
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek')
-rw-r--r--src/soc/mediatek/mt8173/dramc_pi_basic_api.c2
-rw-r--r--src/soc/mediatek/mt8173/dramc_pi_calibration_api.c4
-rw-r--r--src/soc/mediatek/mt8173/mt6391.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
index 4babd542f6..b5826579ba 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
@@ -39,7 +39,7 @@ inline u8 is_dual_rank(u32 channel,
const struct mt8173_sdram_params *sdram_params)
{
/* judge ranks from EMI_CONA[17] (cha) and EMI_CONA[16] (chb) */
- return (sdram_params->emi_set.cona & (1 << (17 - channel))) ? 1 : 0;
+ return (sdram_params->emi_set.cona & (1 << (17 - channel))) ? 1 : 0;
}
static void mem_pll_pre_init(u32 channel)
diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
index 8ed82b119f..7a25bfe8a7 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c
@@ -343,7 +343,7 @@ static u8 dqs_gw_coarse_tune_calib(u32 channel, u8 coarse_val)
gw_ret[i] = dqs_gw_test(channel);
/* judge test result */
if (gw_ret[i] != 0)
- return opt_coarse_val[i];
+ return opt_coarse_val[i];
}
/* abnormal test result, set to default coarse tune value */
@@ -747,7 +747,7 @@ u8 rx_datlat_cal(u32 channel, u8 rank,
}
/* Default dle value is set when test error (error recovery).
- * Others, adjusted dle calibration value is set normally.
+ * Others, adjusted dle calibration value is set normally.
*/
set_dle_factor(channel, best_step);
diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c
index 4f6ba32622..ecea693f4f 100644
--- a/src/soc/mediatek/mt8173/mt6391.c
+++ b/src/soc/mediatek/mt8173/mt6391.c
@@ -86,7 +86,7 @@ static void mt6391_configure_vcama(enum ldo_voltage vsel)
mt6391_write(PMIC_RG_ANALDO_CON6, vsel - 2, PMIC_RG_VCAMA_VOSEL_MASK,
PMIC_RG_VCAMA_VOSEL_SHIFT);
mt6391_write(PMIC_RG_ANALDO_CON2, 1, PMIC_RG_VCAMA_EN_MASK,
- PMIC_RG_VCAMA_EN_SHIFT);
+ PMIC_RG_VCAMA_EN_SHIFT);
}
void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)