arm(64): Replace write32() and friends with writel()

This patch is a raw application of the following spatch to the
directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>,
src/soc/<arm(64)-soc> and src/drivers/gic:

@@
expression A, V;
@@
- write32(V, A)
+ writel(V, A)
@@
expression A, V;
@@
- write16(V, A)
+ writew(V, A)
@@
expression A, V;
@@
- write8(V, A)
+ writeb(V, A)

This replaces all uses of write{32,16,8}() with write{l,w,b}()
which is currently equivalent and much more common. This is a
preparatory step that will allow us to easier flip them all at once to
the new write32(a,v) model.

BRANCH=none
BUG=chromium:451388
TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky.

Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24
Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254862
Reviewed-on: http://review.coreboot.org/9834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 6 insertions, 6 deletions

diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c
index 6f9142ca6d..b9a5f42a37 100644
--- a/src/soc/nvidia/tegra/i2c.c
+++ b/src/soc/nvidia/tegra/i2c.c
@@ -40,9 +40,9 @@ static void do_bus_clear(int bus)
 	// 4. Set TERMINATE condition (1 = IMMEDIATE)
 	bc = read32(&regs->bus_clear_config);
 	bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE;
-	write32(bc, &regs->bus_clear_config);
+	writel(bc, &regs->bus_clear_config);
 	// 4.1 Set MSTR_CONFIG_LOAD and wait for clear
-	write32(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load);
+	writel(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load);
 	for (i = 0; i < timeout_ms * 10 && (read32(&regs->config_load) &
 			I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE); i++) {
 		printk(BIOS_DEBUG, "%s: wait for MSTR_CONFIG_LOAD to clear\n",
@@ -50,7 +50,7 @@ static void do_bus_clear(int bus)
 		udelay(100);
 	}
 	// 5. Set ENABLE to start the bus clear op
-	write32(bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE, &regs->bus_clear_config);
+	writel(bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE, &regs->bus_clear_config);
 	for (i = 0; i < timeout_ms * 10 && (read32(&regs->bus_clear_config) &
 			I2C_BUS_CLEAR_CONFIG_BC_ENABLE); i++) {
 		printk(BIOS_DEBUG, "%s: wait for bus clear completion\n",
@@ -74,7 +74,7 @@ static int tegra_i2c_send_recv(int bus, int read,
 		rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT;
 
 		while (header_words && tx_empty) {
-			write32(*headers++, &regs->tx_packet_fifo);
+			writel(*headers++, &regs->tx_packet_fifo);
 			header_words--;
 			tx_empty--;
 		}
@@ -96,7 +96,7 @@ static int tegra_i2c_send_recv(int bus, int read,
 					int todo = MIN(data_len, sizeof(word));
 
 					memcpy(&word, data, todo);
-					write32(word, &regs->tx_packet_fifo);
+					writel(word, &regs->tx_packet_fifo);
 					data_len -= todo;
 					data += sizeof(word);
 					tx_empty--;
@@ -208,5 +208,5 @@ void i2c_init(unsigned bus)
 {
 	struct tegra_i2c_regs * const regs = tegra_i2c_info[bus].base;
 
-	write32(I2C_CNFG_PACKET_MODE_EN, &regs->cnfg);
+	writel(I2C_CNFG_PACKET_MODE_EN, &regs->cnfg);
 }