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authorJimmy Zhang <jimmzhang@nvidia.com>2014-07-02 17:45:18 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-02-17 01:16:34 +0100
commitb365530bb6341cad601532e43fc899f56ba57acb (patch)
tree4d936234624b6cbe9921c534823ea5469f4386d8 /src/soc/nvidia/tegra124/clock.c
parentb4fa3fd2aedc2d02c973c664a218e5551b4118a1 (diff)
downloadcoreboot-b365530bb6341cad601532e43fc899f56ba57acb.tar.xz
tegra124: Correct cpu power on sequence and CPUPWRGOOD_TIME
Based on TRM, cpu clock enabling and reset vector setting should all be done properly before ungating cpu power partition. Otherwise, with current code, a race condition could occur where cpu starts but reset vector has not been set. BUG=chrome-os-partner:30064 BRANCH=none TEST=run nyan_big reboot test. No issue is experienced. Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Change-Id: I571e128693bb2763ee673bd183b8cf60921dc475 Original-Reviewed-on: https://chromium-review.googlesource.com/206682 Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com> (cherry picked from commit 106480ff32406c899a24544fdfab858db5afd1d9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I3da6018dd68e4c15d2c58db566a9745b0b26c365 Reviewed-on: http://review.coreboot.org/8414 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra124/clock.c')
-rw-r--r--src/soc/nvidia/tegra124/clock.c15
1 files changed, 10 insertions, 5 deletions
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index af2f96a5db..e3c0e71a7e 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -480,7 +480,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
udelay(IO_STABILIZATION_DELAY);
}
-void clock_cpu0_config_and_reset(void *entry)
+void clock_cpu0_config(void *entry)
{
void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100;
@@ -511,7 +511,10 @@ void clock_cpu0_config_and_reset(void *entry)
setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU);
setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG);
setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPULP);
+}
+void clock_cpu0_remove_reset(void)
+{
// Disable the reset on the non-CPU parts of the fast cluster.
write32(CRC_RST_CPUG_CLR_NONCPU,
&clk_rst->rst_cpug_cmplx_clr);
@@ -559,10 +562,12 @@ void clock_init(void)
/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
* features section in the TRM). */
- write32(1 << HCLK_DIVISOR_SHIFT | 0 << PCLK_DIVISOR_SHIFT,
- &clk_rst->clk_sys_rate); /* pclk = hclk = sclk/2 */
- write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, 300000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_CLKEN | PLL_OUT_RSTN, &clk_rst->pllc_out);
+ write32(TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT |
+ TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT,
+ &clk_rst->clk_sys_rate);
+ write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) <<
+ PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN |
+ PLL_OUT_RSTN, &clk_rst->pllc_out);
write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT |
SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
&clk_rst->sclk_brst_pol); /* sclk = 300 MHz */