diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/nvidia/tegra124/dma.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
| download | coreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/nvidia/tegra124/dma.c')
| -rw-r--r-- | src/soc/nvidia/tegra124/dma.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index 761bb6bce5..78a8d10e00 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -82,7 +82,7 @@ struct apb_dma_channel * const dma_claim(void) * Set global enable bit, otherwise register access to channel * DMA registers will not be possible. */ - setbits_le32(&apb_dma->command, APB_COMMAND_GEN); + setbits32(&apb_dma->command, APB_COMMAND_GEN); for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) { regs = apb_dma_channels[i].regs; @@ -122,7 +122,7 @@ void dma_release(struct apb_dma_channel * const channel) return; } - clrbits_le32(&apb_dma->command, APB_COMMAND_GEN); + clrbits32(&apb_dma->command, APB_COMMAND_GEN); } int dma_start(struct apb_dma_channel * const channel) @@ -130,7 +130,7 @@ int dma_start(struct apb_dma_channel * const channel) struct apb_dma_channel_regs *regs = channel->regs; /* Set ENB bit for this channel */ - setbits_le32(®s->csr, APB_CSR_ENB); + setbits32(®s->csr, APB_CSR_ENB); return 0; } @@ -140,7 +140,7 @@ int dma_stop(struct apb_dma_channel * const channel) struct apb_dma_channel_regs *regs = channel->regs; /* Clear ENB bit for this channel */ - clrbits_le32(®s->csr, APB_CSR_ENB); + clrbits32(®s->csr, APB_CSR_ENB); return 0; } |