diff options
| author | Julius Werner <jwerner@chromium.org> | 2016-02-17 16:12:46 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-03-08 22:04:22 +0100 |
| commit | f5452085979d9031023b1b810abf0493757e6287 (patch) | |
| tree | 19eefbef443cd649d3d013e7129f9286135f64cc /src/soc/nvidia/tegra124/include/soc | |
| parent | 61980af95d4c7977bed6a8e353a3d56dd4305bc6 (diff) | |
| download | coreboot-f5452085979d9031023b1b810abf0493757e6287.tar.xz | |
nyan: Fix timestamps and CBFS SPI integration
Nyan is an old board that was committed before several core code
modernizations to timestamp and CBFS code. Not all of those later
patches were correctly integrated with old boards like this, and the
core code has evolved to a point where it doesn't actually boot anymore.
This patch fixes that issue and brings the Nyan boards more in line with
how later ARM platforms look.
BRANCH=None
BUG=None
TEST=My Blaze boots again.
Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717
Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/328543
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13832
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/nvidia/tegra124/include/soc')
| -rw-r--r-- | src/soc/nvidia/tegra124/include/soc/memlayout.ld | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index c3f5f4ec42..5bab362396 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -33,7 +33,8 @@ SECTIONS STACK(0x4000E000, 8K) BOOTBLOCK(0x40010000, 24K) VERSTAGE(0x40016000, 72K) - ROMSTAGE(0x40028000, 96K) + ROMSTAGE(0x40028000, 95K) + TIMESTAMP(0x4003FC00, 1K) SRAM_END(0x40040000) DRAM_START(0x80000000) |