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authorGabe Black <gabeblack@google.com>2014-03-03 16:26:11 -0800
committerMarc Jones <marc.jones@se-eng.com>2014-11-13 06:24:54 +0100
commit317850348e4a16b5b7d762941351e669962a5035 (patch)
tree26536fc343bd0b0bdfe2dc1a2ae7e90cff2977bf /src/soc/nvidia/tegra124/include
parent6940c0da9bab9c0842228053767ac97316dd7c53 (diff)
downloadcoreboot-317850348e4a16b5b7d762941351e669962a5035.tar.xz
tegra124: Make the PLLX frequency selectable by model.
The PLLX provides the clock for the main cores which can run at different max frequencies depending on the specific model of Tegra124. This change makes it possible to select a model which will, in turn, select a frequency for PLLX. The default is 2GHz which is the lowest maximum frequency. BUG=chrome-os-partner:25467 TEST=Booted on nyan rev1. Verified that the selected PLLX frequency was 2GHz. With a change that selects the right model for nyan, verified that the corresponding frequency was selected. BRANCH=None Original-Change-Id: Iee3a615083dee97ad659ff41cbf867af2a0c325d Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/188602 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 1282015048420a518e6c6959ce982be70378211a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I448a830f3184ad1afeadbd1c2974c7a27b03a923 Reviewed-on: http://review.coreboot.org/7409 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/soc/nvidia/tegra124/include')
-rw-r--r--src/soc/nvidia/tegra124/include/soc/clock.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h
index 89be88b020..9f3f0a48d9 100644
--- a/src/soc/nvidia/tegra124/include/soc/clock.h
+++ b/src/soc/nvidia/tegra124/include/soc/clock.h
@@ -238,7 +238,7 @@ enum clock_source { /* Careful: Not true for all sources, always check TRM! */
/* soc-specific */
#define TEGRA_CLK_M_KHZ clock_get_osc_khz()
-#define TEGRA_PLLX_KHZ (1900000)
+#define TEGRA_PLLX_KHZ CONFIG_PLLX_KHZ
#define TEGRA_PLLP_KHZ (408000)
#define TEGRA_PLLC_KHZ (600000)
#define TEGRA_PLLD_KHZ (925000)