tegra124/nyan: rougly stable code base

nyan: Clock setup.
Reviewed-on: https://chromium-review.googlesource.com/172106
(cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1)

tegra124: Call into the mainboard bootblock init if one exists.
Reviewed-on: https://chromium-review.googlesource.com/172581
(cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec)

nyan: Add a mainboard specific bootblock.
Reviewed-on: https://chromium-review.googlesource.com/172582
(cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69)

nyan: tegra124: Redestribute the clock code between the mainboard and soc.
Reviewed-on: https://chromium-review.googlesource.com/172583
(cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b)

nyan: Initialize the i2c pins and controllers.
Reviewed-on: https://chromium-review.googlesource.com/172584
(cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8)

nyan: Initialize the PMIC.
Reviewed-on: https://chromium-review.googlesource.com/172585
(cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a)

tegra124: add a chip.h and use it in NYAN
Reviewed-on: https://chromium-review.googlesource.com/172773
(cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f)

tegra: Reorder GPIO register accesses to avoid glitching
Reviewed-on: https://chromium-review.googlesource.com/172730
(cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5)

tegra: Turn GPIO wrappers into macros to make them easier to write
Reviewed-on: https://chromium-review.googlesource.com/172731
(cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c)

tegra: Change GPIO functions to allow variable arguments
Reviewed-on: https://chromium-review.googlesource.com/172916
(cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d)

tegra124: Implement starting up the main CPUs.
Reviewed-on: https://chromium-review.googlesource.com/172917
(cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3)

tegra: Simplify the I2C constants.
Reviewed-on: https://chromium-review.googlesource.com/172953
(cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76)

tegra124: Fix SPI base addresses
Reviewed-on: https://chromium-review.googlesource.com/173322
(cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357)

tegra124: Scrub the clock constants.
Reviewed-on: https://chromium-review.googlesource.com/172954
(cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4)

tegra124: add DMA support
Reviewed-on: https://chromium-review.googlesource.com/172951
(cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8)

tegra124: add basic SPI driver
Reviewed-on: https://chromium-review.googlesource.com/172952
(cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429)

tegra124: Add an assembly stub which is run first on the main CPUs.
Reviewed-on: https://chromium-review.googlesource.com/173541
(cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de)

nyan: tegra124: Set up dynamic cbmem.
Reviewed-on: https://chromium-review.googlesource.com/173542
(cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f)

tegra124: Add an soc.c which sets up the chip operations and memory resource.
Reviewed-on: https://chromium-review.googlesource.com/173543
(cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4)

tegra124: extend chip.h to include video settings
Reviewed-on: https://chromium-review.googlesource.com/173600
(cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29)

tegra124 and nyan: fill in the devicetree a bit more, add defines
Reviewed-on: https://chromium-review.googlesource.com/173684
(cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147)

tegra124: clean-ups for SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173599
(cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7)

tegra124: add a #define for DMA alignment size
Reviewed-on: https://chromium-review.googlesource.com/173638
(cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af)

tegra124: Add FIFO transmit functions to SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173639
(cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7)

tegra124: clean-ups for DMA driver
Reviewed-on: https://chromium-review.googlesource.com/173598
(cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0)

tegra124: early display and display code.
Reviewed-on: https://chromium-review.googlesource.com/173622
(cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558)

tegra124: Move transfer size handling to spi_xfer()
Reviewed-on: https://chromium-review.googlesource.com/173680
(cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621)

tegra124: strict error detection and reporting for SPI
Reviewed-on: https://chromium-review.googlesource.com/173681
(cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010)

tegra124: add thread-friendly delays to SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173648
(cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e)

Tegra124: Take the SPI1 controller out of reset and enable its clock.
Reviewed-on: https://chromium-review.googlesource.com/173787
(cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2)

tegra124: add two more clock setting values
Reviewed-on: https://chromium-review.googlesource.com/173772
(cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57)

nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC.
Reviewed-on: https://chromium-review.googlesource.com/173788
(cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8)

tegra124: Add some stub functions to the Tegra SPI driver.
Reviewed-on: https://chromium-review.googlesource.com/173789
(cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2)

tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS.
Reviewed-on: https://chromium-review.googlesource.com/173790
(cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084)

nyan: Implement the code which reads GPIOs for ChromeOS.
Reviewed-on: https://chromium-review.googlesource.com/173791
(cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3)

nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options.
Reviewed-on: https://chromium-review.googlesource.com/173792
(cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e)

Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks.
Reviewed-on: https://chromium-review.googlesource.com/173793
(cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88)

tegra124: fix clear_fifo_status() in SPI driver
Reviewed-on: https://chromium-review.googlesource.com/173738
(cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f)

ARM: Include stdint.h in cpu.h.
Reviewed-on: https://chromium-review.googlesource.com/173774
(cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6)

tegra124: When setting up the main CPU, set its CPSR appropriately.
Reviewed-on: https://chromium-review.googlesource.com/173775
(cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead)

tegra124: fix wrong names in clk_rst.h
Reviewed-on: https://chromium-review.googlesource.com/173955
(cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d)

tegra124: Fix up the PLLX divider table.
Reviewed-on: https://chromium-review.googlesource.com/173778
(cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17)

tegra124: clock: Get rid of cpcon and dccon.
Reviewed-on: https://chromium-review.googlesource.com/173779
(cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7)

Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus.
Reviewed-on: https://chromium-review.googlesource.com/173953
(cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355)

armv7: expose dcache_line_bytes() in cache API
Reviewed-on: https://chromium-review.googlesource.com/173975
(cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12)

libpayload: expose dcache_line_bytes() in ARM cache API
Reviewed-on: https://chromium-review.googlesource.com/174099
(cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9)

armv4: add a stub for dcache_line_bytes()
Reviewed-on: https://chromium-review.googlesource.com/173976
(cherry picked from commit 924f61ea895b9268c716791466637009bbac6469)

tegra124: Base early UART on CLK_M to enable debugging of PLL init code
Reviewed-on: https://chromium-review.googlesource.com/174339
(cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa)

tegra124: Add additional PLLs and redesign the divisor table
Reviewed-on: https://chromium-review.googlesource.com/174380
(cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384)

Squashed 49 commits for tegra124/nyan that included a lot of churn on
different pieces.

Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6869
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

3 files changed, 209 insertions, 6 deletions

diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h
index bf59d75085..98362156d2 100644
--- a/src/soc/nvidia/tegra124/include/soc/addressmap.h
+++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h
@@ -21,6 +21,8 @@
 #ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__
 #define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__
 
+#include <stddef.h>
+
 enum {
 	TEGRA_SRAM_BASE = 0x40000000,
 	TEGRA_SRAM_SIZE = 0x20000
@@ -28,12 +30,15 @@ enum {
 
 enum {
 	TEGRA_ARM_PERIPHBASE =		0x50040000,
+	TEGRA_ARM_DISPLAYA =            0x54200000,
+	TEGRA_ARM_DISPLAYB =            0x54240000,
 	TEGRA_PG_UP_BASE =		0x60000000,
 	TEGRA_TMRUS_BASE =		0x60005010,
 	TEGRA_CLK_RST_BASE =		0x60006000,
 	TEGRA_FLOW_BASE =		0x60007000,
 	TEGRA_GPIO_BASE =		0x6000D000,
 	TEGRA_EVP_BASE =		0x6000F000,
+	TEGRA_APB_DMA_BASE =		0x60020000,
 	TEGRA_APB_MISC_BASE =		0x70000000,
 	TEGRA_APB_MISC_GP_BASE =	TEGRA_APB_MISC_BASE + 0x0800,
 	TEGRA_APB_PINGROUP_BASE =	TEGRA_APB_MISC_BASE + 0x0868,
@@ -51,12 +56,12 @@ enum {
 	TEGRA_I2C4_BASE =		TEGRA_APB_MISC_BASE + 0xC700,
 	TEGRA_I2C5_BASE =		TEGRA_APB_MISC_BASE + 0xD000,
 	TEGRA_I2C6_BASE =		TEGRA_APB_MISC_BASE + 0xD100,
-	TEGRA_SLINK1_BASE =		TEGRA_APB_MISC_BASE + 0xD400,
-	TEGRA_SLINK2_BASE =		TEGRA_APB_MISC_BASE + 0xD600,
-	TEGRA_SLINK3_BASE =		TEGRA_APB_MISC_BASE + 0xD800,
-	TEGRA_SLINK4_BASE =		TEGRA_APB_MISC_BASE + 0xDA00,
-	TEGRA_SLINK5_BASE =		TEGRA_APB_MISC_BASE + 0xDC00,
-	TEGRA_SLINK6_BASE =		TEGRA_APB_MISC_BASE + 0xDE00,
+	TEGRA_SPI1_BASE =		TEGRA_APB_MISC_BASE + 0xD400,
+	TEGRA_SPI2_BASE =		TEGRA_APB_MISC_BASE + 0xD600,
+	TEGRA_SPI3_BASE =		TEGRA_APB_MISC_BASE + 0xD800,
+	TEGRA_SPI4_BASE =		TEGRA_APB_MISC_BASE + 0xDA00,
+	TEGRA_SPI5_BASE =		TEGRA_APB_MISC_BASE + 0xDC00,
+	TEGRA_SPI6_BASE =		TEGRA_APB_MISC_BASE + 0xDE00,
 	TEGRA_DVC_BASE =		TEGRA_APB_MISC_BASE + 0xD000,
 	TEGRA_PMC_BASE =		TEGRA_APB_MISC_BASE + 0xE400,
 	TEGRA_EMC_BASE =		TEGRA_APB_MISC_BASE + 0xF400,
@@ -69,4 +74,9 @@ enum {
 	TEGRA_I2C_BASE_COUNT = 6,
 };
 
+enum {
+	FB_SIZE_MB = (32),
+	FB_BASE_MB = (CONFIG_SYS_SDRAM_BASE/MiB + (CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)),
+};
+
 #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */
diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h
new file mode 100644
index 0000000000..056a38b2e0
--- /dev/null
+++ b/src/soc/nvidia/tegra124/include/soc/clock.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA124_CLOCK_H__
+#define __SOC_NVIDIA_TEGRA124_CLOCK_H__
+
+enum {
+	CLK_L_CPU = 0x1 << 0,
+	CLK_L_COP = 0x1 << 1,
+	CLK_L_TRIG_SYS = 0x1 << 2,
+	CLK_L_RTC = 0x1 << 4,
+	CLK_L_TMR = 0x1 << 5,
+	CLK_L_UARTA = 0x1 << 6,
+	CLK_L_UARTB = 0x1 << 7,
+	CLK_L_GPIO = 0x1 << 8,
+	CLK_L_SDMMC2 = 0x1 << 9,
+	CLK_L_SPDIF = 0x1 << 10,
+	CLK_L_I2S1 = 0x1 << 11,
+	CLK_L_I2C1 = 0x1 << 12,
+	CLK_L_NDFLASH = 0x1 << 13,
+	CLK_L_SDMMC1 = 0x1 << 14,
+	CLK_L_SDMMC4 = 0x1 << 15,
+	CLK_L_PWM = 0x1 << 17,
+	CLK_L_I2S2 = 0x1 << 18,
+	CLK_L_EPP = 0x1 << 19,
+	CLK_L_VI = 0x1 << 20,
+	CLK_L_2D = 0x1 << 21,
+	CLK_L_USBD = 0x1 << 22,
+	CLK_L_ISP = 0x1 << 23,
+	CLK_L_3D = 0x1 << 24,
+	CLK_L_DISP2 = 0x1 << 26,
+	CLK_L_DISP1 = 0x1 << 27,
+	CLK_L_HOST1X = 0x1 << 28,
+	CLK_L_VCP = 0x1 << 29,
+	CLK_L_I2S0 = 0x1 << 30,
+	CLK_L_CACHE2 = 0x1 << 31,
+
+	CLK_H_MEM = 0x1 << 0,
+	CLK_H_AHBDMA = 0x1 << 1,
+	CLK_H_APBDMA = 0x1 << 2,
+	CLK_H_KBC = 0x1 << 4,
+	CLK_H_STAT_MON = 0x1 << 5,
+	CLK_H_PMC = 0x1 << 6,
+	CLK_H_FUSE = 0x1 << 7,
+	CLK_H_KFUSE = 0x1 << 8,
+	CLK_H_SBC1 = 0x1 << 9,
+	CLK_H_SNOR = 0x1 << 10,
+	CLK_H_JTAG2TBC = 0x1 << 11,
+	CLK_H_SBC2 = 0x1 << 12,
+	CLK_H_SBC3 = 0x1 << 14,
+	CLK_H_I2C5 = 0x1 << 15,
+	CLK_H_DSI = 0x1 << 16,
+	CLK_H_HSI = 0x1 << 18,
+	CLK_H_HDMI = 0x1 << 19,
+	CLK_H_CSI = 0x1 << 20,
+	CLK_H_I2C2 = 0x1 << 22,
+	CLK_H_UARTC = 0x1 << 23,
+	CLK_H_MIPI_CAL = 0x1 << 24,
+	CLK_H_EMC = 0x1 << 25,
+	CLK_H_USB2 = 0x1 << 26,
+	CLK_H_USB3 = 0x1 << 27,
+	CLK_H_MPE = 0x1 << 28,
+	CLK_H_VDE = 0x1 << 29,
+	CLK_H_BSEA = 0x1 << 30,
+	CLK_H_BSEV = 0x1 << 31,
+
+	CLK_U_UARTD = 0x1 << 1,
+	CLK_U_UARTE = 0x1 << 2,
+	CLK_U_I2C3 = 0x1 << 3,
+	CLK_U_SBC4 = 0x1 << 4,
+	CLK_U_SDMMC3 = 0x1 << 5,
+	CLK_U_PCIE = 0x1 << 6,
+	CLK_U_OWR = 0x1 << 7,
+	CLK_U_AFI = 0x1 << 8,
+	CLK_U_CSITE = 0x1 << 9,
+	CLK_U_PCIEXCLK = 0x1 << 10,
+	CLK_U_AVPUCQ = 0x1 << 11,
+	CLK_U_TRACECLKIN = 0x1 << 13,
+	CLK_U_SOC_THERM = 0x1 << 14,
+	CLK_U_DTV = 0x1 << 15,
+	CLK_U_NAND_SPEED = 0x1 << 16,
+	CLK_U_I2C_SLOW = 0x1 << 17,
+	CLK_U_DSIB = 0x1 << 18,
+	CLK_U_TSEC = 0x1 << 19,
+	CLK_U_IRAMA = 0x1 << 20,
+	CLK_U_IRAMB = 0x1 << 21,
+	CLK_U_IRAMC = 0x1 << 22,
+
+	// Clock reset.
+	CLK_U_EMUCIF = 0x1 << 23,
+	// Clock enable.
+	CLK_U_IRAMD = 0x1 << 23,
+
+	CLK_U_CRAM2 = 0x2 << 24,
+	CLK_U_XUSB_HOST = 0x1 << 25,
+	CLK_U_MSENC = 0x1 << 27,
+	CLK_U_SUS_OUT = 0x1 << 28,
+	CLK_U_DEV2_OUT = 0x1 << 29,
+	CLK_U_DEV1_OUT = 0x1 << 30,
+	CLK_U_XUSB_DEV = 0x1 << 31,
+
+	CLK_V_CPUG = 0x1 << 0,
+	CLK_V_CPULP = 0x1 << 1,
+	CLK_V_3D2 = 0x1 << 2,
+	CLK_V_MSELECT = 0x1 << 3,
+	CLK_V_I2S3 = 0x1 << 5,
+	CLK_V_I2S4 = 0x1 << 6,
+	CLK_V_I2C4 = 0x1 << 7,
+	CLK_V_SBC5 = 0x1 << 8,
+	CLK_V_SBC6 = 0x1 << 9,
+	CLK_V_AUDIO = 0x1 << 10,
+	CLK_V_APBIF = 0x1 << 11,
+	CLK_V_DAM0 = 0x1 << 12,
+	CLK_V_DAM1 = 0x1 << 13,
+	CLK_V_DAM2 = 0x1 << 14,
+	CLK_V_HDA2CODEC_2X = 0x1 << 15,
+	CLK_V_ATOMICS = 0x1 << 16,
+	CLK_V_ACTMON = 0x1 << 23,
+	CLK_V_SATA = 0x1 << 28,
+	CLK_V_HDA = 0x1 << 29,
+
+	CLK_W_HDA2HDMICODEC = 0x1 << 0,
+	CLK_W_SATACOLD = 0x1 << 1,
+	CLK_W_CEC = 0x1 << 8,
+	CLK_W_XUSB_PADCTL = 0x1 << 14,
+	CLK_W_ENTROPY = 0x1 << 21,
+	CLK_W_AMX0 = 0x1 << 25,
+	CLK_W_ADX0 = 0x1 << 26,
+	CLK_W_DVFS = 0x1 << 27,
+	CLK_W_XUSB_SS = 0x1 << 28,
+	CLK_W_MC1 = 0x1 << 30,
+	CLK_W_EMC1 = 0x1 << 31
+};
+
+/* PLL stabilization delay in usec */
+#define CLOCK_PLL_STABLE_DELAY_US 300
+
+#define IO_STABILIZATION_DELAY (2)
+/* Calculate clock fractional divider value from ref and target frequencies */
+#define CLK_DIVIDER(REF, FREQ)	((((REF) * 2) / FREQ) - 2)
+
+/* Calculate clock frequency value from reference and clock divider value */
+#define CLK_FREQUENCY(REF, REG)	(((REF) * 2) / (REG + 2))
+
+/* soc-specific */
+#define TEGRA_PLLX_KHZ   (1900000)
+#define TEGRA_PLLP_KHZ   (408000)
+#define TEGRA_PLLC_KHZ   (600000)
+#define TEGRA_PLLD_KHZ   (925000)
+#define TEGRA_PLLU_KHZ   (960000)
+
+int clock_get_osc_khz(void);
+void clock_early_uart(void);
+void clock_cpu0_config_and_reset(void * entry);
+void clock_config(void);
+void clock_init(void);
+void clock_ll_set_source_divisor(u32 *reg, u32 source, u32 divisor);
+#endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */
diff --git a/src/soc/nvidia/tegra124/include/soc/display.h b/src/soc/nvidia/tegra124/include/soc/display.h
new file mode 100644
index 0000000000..8c7e3e7b17
--- /dev/null
+++ b/src/soc/nvidia/tegra124/include/soc/display.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__
+#define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__
+
+void setup_display(struct soc_nvidia_tegra124_config *config);
+
+#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */