tegra124/nyan: memory and display updates

tegra124: use pll_c_out1 as sclk parent
Reviewed-on: https://chromium-review.googlesource.com/180865
(cherry picked from commit 418337a5bde70df6a770222201c51bf3e8892d5f)

tegra124: take LP cluster out of reset
Reviewed-on: https://chromium-review.googlesource.com/180866
(cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3)

tegra124: norrin: display code clean up
Reviewed-on: https://chromium-review.googlesource.com/181003
(cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17)

tegra124: Change the display hack to use window A
Reviewed-on: https://chromium-review.googlesource.com/182001
(cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a)

tegra124: norrin: Initialize frame buffer
Reviewed-on: https://chromium-review.googlesource.com/182090
(cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167)

nyan: do not enable pull-ups on SPI1 (EC) data pins
Reviewed-on: https://chromium-review.googlesource.com/181063
(cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c)

tegra124: Add source for the LP0 resume blob.
Reviewed-on: https://chromium-review.googlesource.com/183152
(cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b)

tegra124: Revise Memory Controller registers structure definition.
Reviewed-on: https://chromium-review.googlesource.com/182992
(cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1)

tegra124: Add more PMC register details.
Reviewed-on: https://chromium-review.googlesource.com/183231
(cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829)

tegra124: Add SDRAM configuration header file from cbootimage.
Reviewed-on: https://chromium-review.googlesource.com/182613
(cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4)

tegra124: Revise sdram_param.h for Coreboot.
Reviewed-on: https://chromium-review.googlesource.com/182614
(cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8)

tegra124: Fix EMC base address.
Reviewed-on: https://chromium-review.googlesource.com/183602
(cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e)

tegra124: Add EMC registers definition.
Reviewed-on: https://chromium-review.googlesource.com/183622
(cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a)

tegra124: Never touch MEM(MC)/EMC clocks in ramstage.
Reviewed-on: https://chromium-review.googlesource.com/183623
(cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023)

tegra124: use RAM_CODE[3:2] for ram code
Reviewed-on: https://chromium-review.googlesource.com/183833
(cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d)

tegra124: Allow setting PLLM (clock for SDRAM).
Reviewed-on: https://chromium-review.googlesource.com/183621
(cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683)

tegra124: SDRAM Initialization.
Reviewed-on: https://chromium-review.googlesource.com/182615
(cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce)

tegra124: Get RAM_CODE for SDRAM initialization.
Reviewed-on: https://chromium-review.googlesource.com/183781
(cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8)

Squashed 18 nyan/tegra commits for memory and display.

Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6914
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

1 files changed, 104 insertions, 23 deletions

diff --git a/src/soc/nvidia/tegra124/mc.h b/src/soc/nvidia/tegra124/mc.h
index 92a38ed95f..0fc3738746 100644
--- a/src/soc/nvidia/tegra124/mc.h
+++ b/src/soc/nvidia/tegra124/mc.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2010 - 2013, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2013 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -14,34 +15,114 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef _TEGRA124_MC_H_
-#define _TEGRA124_MC_H_
+#ifndef __SOC_NVIDIA_TEGRA124_MC_H__
+#define __SOC_NVIDIA_TEGRA124_MC_H__
 
+#include <stddef.h>
 #include <stdint.h>
 
 // Memory Controller registers we need/care about
 
 struct tegra_mc_regs {
-	u32 reserved0[4];
-	u32 mc_smmu_config;
-	u32 mc_smmu_tlb_config;
-	u32 mc_smmu_ptc_config;
-	u32 mc_smmu_ptb_asid;
-	u32 mc_smmu_ptb_data;
-	u32 reserved1[3];
-	u32 mc_smmu_tlb_flush;
-	u32 mc_smmu_ptc_flush;
-	u32 reserved2[6];
-	u32 mc_emem_cfg;
-	u32 mc_emem_adr_cfg;
-	u32 mc_emem_adr_cfg_dev0;
-	u32 mc_emem_adr_cfg_dev1;
-	u32 reserved3[12];
-	u32 mc_emem_arb_reserved[28];
-	u32 reserved4[338];
-	u32 mc_vpr_bom;
-	u32 mc_vpr_size;
-	u32 mc_vpr_ctrl;
+	uint32_t rsvd_0x0[4];			/* 0x00 */
+	uint32_t smmu_config;			/* 0x10 */
+	uint32_t smmu_tlb_config;		/* 0x14 */
+	uint32_t smmu_ptc_config;		/* 0x18 */
+	uint32_t smmu_ptb_asid;			/* 0x1c */
+	uint32_t smmu_ptb_data;			/* 0x20 */
+	uint32_t rsvd_0x24[3];			/* 0x24 */
+	uint32_t smmu_tlb_flush;		/* 0x30 */
+	uint32_t smmu_ptc_flush;		/* 0x34 */
+	uint32_t rsvd_0x38[6];			/* 0x38 */
+	uint32_t emem_cfg;			/* 0x50 */
+	uint32_t emem_adr_cfg;			/* 0x54 */
+	uint32_t emem_adr_cfg_dev0;		/* 0x58 */
+	uint32_t emem_adr_cfg_dev1;		/* 0x5c */
+	uint32_t rsvd_0x60[1];			/* 0x60 */
+	uint32_t emem_adr_cfg_bank_mask_0;	/* 0x64 */
+	uint32_t emem_adr_cfg_bank_mask_1;	/* 0x68 */
+	uint32_t emem_adr_cfg_bank_mask_2;	/* 0x6c */
+	uint32_t rsvd_0x70[8];			/* 0x70 */
+	uint32_t emem_arb_cfg;			/* 0x90 */
+	uint32_t emem_arb_outstanding_req;	/* 0x94 */
+	uint32_t emem_arb_timing_rcd;		/* 0x98 */
+	uint32_t emem_arb_timing_rp;		/* 0x9c */
+	uint32_t emem_arb_timing_rc;		/* 0xa0 */
+	uint32_t emem_arb_timing_ras;		/* 0xa4 */
+	uint32_t emem_arb_timing_faw;		/* 0xa8 */
+	uint32_t emem_arb_timing_rrd;		/* 0xac */
+	uint32_t emem_arb_timing_rap2pre;	/* 0xb0 */
+	uint32_t emem_arb_timing_wap2pre;	/* 0xb4 */
+	uint32_t emem_arb_timing_r2r;		/* 0xb8 */
+	uint32_t emem_arb_timing_w2w;		/* 0xbc */
+	uint32_t emem_arb_timing_r2w;		/* 0xc0 */
+	uint32_t emem_arb_timing_w2r;		/* 0xc4 */
+	uint32_t rsvd_0xc8[2];			/* 0xc8 */
+	uint32_t emem_arb_da_turns;		/* 0xd0 */
+	uint32_t emem_arb_da_covers;		/* 0xd4 */
+	uint32_t emem_arb_misc0;		/* 0xd8 */
+	uint32_t emem_arb_misc1;		/* 0xdc */
+	uint32_t emem_arb_ring1_throttle;	/* 0xe0 */
+	uint32_t emem_arb_ring3_throttle;	/* 0xe4 */
+	uint32_t emem_arb_override;		/* 0xe8 */
+	uint32_t emem_arb_rsv;			/* 0xec */
+	uint32_t rsvd_0xf0[1];			/* 0xf0 */
+	uint32_t clken_override;		/* 0xf4 */
+	uint32_t timing_control_dbg;		/* 0xf8 */
+	uint32_t timing_control;		/* 0xfc */
+	uint32_t stat_control;			/* 0x100 */
+	uint32_t rsvd_0x104[65];		/* 0x104 */
+	uint32_t emem_arb_isochronous_0;	/* 0x208 */
+	uint32_t emem_arb_isochronous_1;	/* 0x20c */
+	uint32_t emem_arb_isochronous_2;	/* 0x210 */
+	uint32_t rsvd_0x214[38];		/* 0x214 */
+	uint32_t dis_extra_snap_levels;		/* 0x2ac */
+	uint32_t rsvd_0x2b0[90];		/* 0x2b0 */
+	uint32_t video_protect_vpr_override;	/* 0x418 */
+	uint32_t rsvd_0x41c[93];		/* 0x41c */
+	uint32_t video_protect_vpr_override1;	/* 0x590 */
+	uint32_t rsvd_0x594[29];		/* 0x594 */
+	uint32_t display_snap_ring;		/* 0x608 */
+	uint32_t rsvd_0x60c[15];		/* 0x60c */
+	uint32_t video_protect_bom;		/* 0x648 */
+	uint32_t video_protect_size_mb;		/* 0x64c */
+	uint32_t video_protect_reg_ctrl;	/* 0x650 */
+	uint32_t rsvd_0x654[4];			/* 0x654 */
+	uint32_t emem_cfg_access_ctrl;		/* 0x664 */
+	uint32_t rsvd_0x668[2];			/* 0x668 */
+	uint32_t sec_carveout_bom;		/* 0x670 */
+	uint32_t sec_carveout_size_mb;		/* 0x674 */
+	uint32_t sec_carveout_reg_ctrl;		/* 0x678 */
+	uint32_t rsvd_0x67c[187];		/* 0x67c */
+	uint32_t emem_arb_override_1;		/* 0x968 */
+	uint32_t rsvd_0x96c[3];			/* 0x96c */
+	uint32_t video_protect_bom_adr_hi;	/* 0x978 */
+	uint32_t rsvd_0x97c[2];			/* 0x97c */
+	uint32_t video_protect_gpu_override_0;	/* 0x984 */
+	uint32_t video_protect_gpu_override_1;	/* 0x988 */
+	uint32_t rsvd_0x98c[5];			/* 0x98c */
+	uint32_t mts_carveout_bom;		/* 0x9a0 */
+	uint32_t mts_carveout_size_mb;		/* 0x9a4 */
+	uint32_t mts_carveout_adr_hi;		/* 0x9a8 */
+	uint32_t mts_carveout_reg_ctrl;		/* 0x9ac */
+	uint32_t rsvd_0x9b0[4];			/* 0x9b0 */
+	uint32_t emem_bank_swizzle_cfg0;	/* 0x9c0 */
+	uint32_t emem_bank_swizzle_cfg1;	/* 0x9c4 */
+	uint32_t emem_bank_swizzle_cfg2;	/* 0x9c8 */
+	uint32_t emem_bank_swizzle_cfg3;	/* 0x9cc */
+	uint32_t rsvd_0x9d0[1];			/* 0x9d0 */
+	uint32_t sec_carveout_adr_hi;		/* 0x9d4 */
 };
 
-#endif	/* _TEGRA124_MC_H_ */
+enum {
+	MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27,
+	MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27,
+
+	MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1,
+
+	MC_TIMING_CONTROL_TIMING_UPDATE = 1,
+};
+
+check_member(tegra_mc_regs, sec_carveout_adr_hi, 0x9d4);
+
+#endif	/* __SOC_NVIDIA_TEGRA124_MC_H__ */