tegra/nyan*: sdram updates

nyan_big: Add 204MHz BCT for bringup, use 1.2V for VDD_CPU
Reviewed-on: https://chromium-review.googlesource.com/183939
(cherry picked from commit a6df76afb5342b805baca749abb8265e15748dc1)

nyan_big: Add initial 792MHz BCT
Reviewed-on: https://chromium-review.googlesource.com/183975
(cherry picked from commit 61d0122fdce6dc9479666bb0a5bc079c6389f78a)

nyan_big: use RAM_CODE[3:2] for ram code
Reviewed-on: https://chromium-review.googlesource.com/184076
(cherry picked from commit 35e5c5e473f871cdc897473a31586afbececd716)

tegra124: support tri-state Board Id
Reviewed-on: https://chromium-review.googlesource.com/183855
(cherry picked from commit 1a9d1bd73aa2cd0c36203b247976ad0d00a360e4)

nyan*: Fix SPI pinmux configuration
Reviewed-on: https://chromium-review.googlesource.com/184281
(cherry picked from commit ac4106b673c285af66d72392bd4a8522aba98489)

nyan_big: Add 4GB 204/792MHz BCTs
Reviewed-on: https://chromium-review.googlesource.com/184159
(cherry picked from commit 5ff002d09f8db0543b58962f6c0d24627fb0937e)

tegra124: Add function for obtaining DRAM size via MC regs
Reviewed-on: https://chromium-review.googlesource.com/184535
(cherry picked from commit d4580c46de649903a266a99eb11c9126ba385b48)

tegra124/nyan*: Obtain DRAM size dynamically
Reviewed-on: https://chromium-review.googlesource.com/184431
(cherry picked from commit a7db71744771decc04cf1966efba70bf4897cfa3)

tegra124: Rearrange iRAM layout to allow more space for romstage
Reviewed-on: https://chromium-review.googlesource.com/184240
(cherry picked from commit 6bdaabbc068146a4516c724b71d31bb777dabcfc)

tegra124: Fix MemoryType field name in SDRAM parameters.
Reviewed-on: https://chromium-review.googlesource.com/185113
(cherry picked from commit 9caccd1e86a8c683402fab87d9f3a49b87496e97)

nyan_big: Initialize SDRAM without BootROM.
Reviewed-on: https://chromium-review.googlesource.com/183624
(cherry picked from commit a1cbc00aa80ec1ea52e833a8e31c8e4b27160e70)

tegra124: move FB_SIZE_MB to a more appropriate location
Reviewed-on: https://chromium-review.googlesource.com/184930
(cherry picked from commit ddea486fd4410394417c4e59039d46a324918bdc)

nyan: Initialize SDRAM without BootROM.
Reviewed-on: https://chromium-review.googlesource.com/185114
(cherry picked from commit 1ff51b580b28553919f91b11b443251b048cf26b)

tegra124: Save SDRAM parameters to PMC registers for LP0
Reviewed-on: https://chromium-review.googlesource.com/182928
(cherry picked from commit 7476b4bd0ecdc312476cce871d22f57915a0bd86)

tegra124: Rewrite SDRAM parameter saving code to be more efficient
Reviewed-on: https://chromium-review.googlesource.com/184388
(cherry picked from commit 25084bd0407624e4b2ff82388c32af1198c501a6)

nyan: Slightly change the way SDRAM parameter files are set up
Reviewed-on: https://chromium-review.googlesource.com/185286
(cherry picked from commit a31887b804f23e031c395113db582cd71f3d1b6d)

Squashed 16 commits for SDRAM support on nyan and nyan_big.

Change-Id: I07419985376277083d62400dd14fe8273f6d5ca8
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6949
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

1 files changed, 30 insertions, 0 deletions

diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c
index 283cbf4998..dcab810a45 100644
--- a/src/soc/nvidia/tegra124/sdram.c
+++ b/src/soc/nvidia/tegra124/sdram.c
@@ -568,6 +568,13 @@ void sdram_init(const struct sdram_params *param)
 	struct tegra_mc_regs *mc = (struct tegra_mc_regs*)TEGRA_MC_BASE;
 	struct tegra_emc_regs *emc = (struct tegra_emc_regs*)TEGRA_EMC_BASE;
 
+	printk(BIOS_DEBUG, "Initializing SDRAM of type %d with %dKHz\n",
+		param->MemoryType, clock_get_osc_khz() *
+		param->PllMFeedbackDivider / param->PllMInputDivider /
+		(1 + param->PllMSelectDiv2));
+	if (param->MemoryType != NvBootMemoryType_Ddr3)
+		die("Unsupported memory type!\n");
+
 	sdram_configure_pmc(param, pmc);
 	sdram_patch(param->EmcBctSpare0, param->EmcBctSpare1);
 
@@ -600,6 +607,8 @@ void sdram_init(const struct sdram_params *param)
 	sdram_set_refresh(param, emc);
 	sdram_enable_arbiter(param);
 	sdram_lock_carveouts(param, mc);
+
+	sdram_lp0_save_params(param);
 }
 
 uint32_t sdram_get_ram_code(void)
@@ -609,3 +618,24 @@ uint32_t sdram_get_ram_code(void)
 		 PMC_STRAPPING_OPT_A_RAM_CODE_MASK) >>
 		PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT);
 }
+
+/* returns total amount of DRAM (in MB) from memory controller registers */
+int sdram_size_mb(void)
+{
+	struct tegra_mc_regs *mc = (struct tegra_mc_regs *)TEGRA_MC_BASE;
+	static int total_size = 0;
+
+	if (total_size)
+		return total_size;
+
+	/*
+	 * This obtains memory size from the External Memory Aperture
+	 * Configuration register. Nvidia confirmed that it is safe to assume
+	 * this value represents the total physical DRAM size.
+	 */
+	total_size = (read32(&mc->emem_cfg) >>
+			MC_EMEM_CFG_SIZE_MB_SHIFT) & MC_EMEM_CFG_SIZE_MB_MASK;
+
+	printk(BIOS_DEBUG, "%s: Total SDRAM (MB): %u\n", __func__, total_size);
+	return total_size;
+}