Add check_member macro to allow clean and easy struct offset checking

This patch adds a new static assertion macro that can be used to check
the offsets in structures that overlay register sets at compile time. It
uses the _Static_assert() declaration from the new ISO C11 standard,
which is supported (even without -std=c11) by GCC after version 4.6.
(There is supposedly also support in clang, although I haven't tried
it... let's deal with compiler issues when/if they turn up.)

I've added it to all structures for our current ARM SoCs for now, and I
think every new register overlay we add going forward should use them
(at least for the last member, but feel free to add more if you think
it's useful).

Change-Id: If32510e7049739ad05618d363a854dc372d64386
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179412
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit cef5fa13c31375a316ca4556c0039b17c8ea7900)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6905
Tested-by: build bot (Jenkins)

6 files changed, 7 insertions, 0 deletions

diff --git a/src/soc/nvidia/tegra124/clk_rst.h b/src/soc/nvidia/tegra124/clk_rst.h
index fb656fb0b3..156e9a69fa 100644
--- a/src/soc/nvidia/tegra124/clk_rst.h
+++ b/src/soc/nvidia/tegra124/clk_rst.h
@@ -295,6 +295,7 @@ struct  __attribute__ ((__packed__)) clk_rst_ctlr {
 	u32 clk_src_emc_latency;	/* _CLK_SOURCE_EMC_LATENCY  0x640 */
 	u32 clk_src_soc_therm;		/* _CLK_SOURCE_SOC_THERM    0x644 */
 };
+check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644);
 
 #define TEGRA_DEV_L			0
 #define TEGRA_DEV_H			1
diff --git a/src/soc/nvidia/tegra124/dma.h b/src/soc/nvidia/tegra124/dma.h
index 557cead6be..e37bf743ad 100644
--- a/src/soc/nvidia/tegra124/dma.h
+++ b/src/soc/nvidia/tegra124/dma.h
@@ -70,6 +70,7 @@ struct apb_dma {
 	u32 chan_wr_reg3;	/* 0x50 */
 	u32 channel_swid1;	/* 0x54 */
 } __attribute__((packed));
+check_member(apb_dma, channel_swid1, 0x54);
 
 /*
  * Naming in the doc included a superfluous _CHANNEL_n_ for
@@ -167,6 +168,7 @@ struct apb_dma_channel_regs {
 	u32 wcount;		/* 0x20 */
 	u32 word_transfer;	/* 0x24 */
 } __attribute__((packed));
+check_member(apb_dma_channel_regs, word_transfer, 0x24);
 
 struct apb_dma_channel {
 	const int num;
diff --git a/src/soc/nvidia/tegra124/flow.h b/src/soc/nvidia/tegra124/flow.h
index f8a1475463..531278c402 100644
--- a/src/soc/nvidia/tegra124/flow.h
+++ b/src/soc/nvidia/tegra124/flow.h
@@ -36,6 +36,7 @@ struct flow_ctlr {
 	u32 mpid;		/* offset 0x3c */
 	u32 ram_repair;		/* offset 0x40 */
 };
+check_member(flow_ctlr, ram_repair, 0x40);
 
 enum {
 	FLOW_MODE_SHIFT = 29,
diff --git a/src/soc/nvidia/tegra124/pmc.h b/src/soc/nvidia/tegra124/pmc.h
index c2e4f4d890..f88e25308c 100644
--- a/src/soc/nvidia/tegra124/pmc.h
+++ b/src/soc/nvidia/tegra124/pmc.h
@@ -156,6 +156,7 @@ struct tegra_pmc_regs {
 	u32 secure_scratch8[24 - 8];
 	u32 scratch56[120 - 56];
 };
+check_member(tegra_pmc_regs, scratch56, 0x340);
 
 enum {
 	PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f,
diff --git a/src/soc/nvidia/tegra124/spi.h b/src/soc/nvidia/tegra124/spi.h
index fa238f2d03..857c35f1b9 100644
--- a/src/soc/nvidia/tegra124/spi.h
+++ b/src/soc/nvidia/tegra124/spi.h
@@ -39,6 +39,7 @@ struct tegra_spi_regs {
 	u32 rx_fifo;		/* 0x188: SPI_FIFO2 */
 	u32 spare_ctl;		/* 0x18c: SPI_SPARE_CTRL */
 } __attribute__((packed));
+check_member(tegra_spi_regs, spare_ctl, 0x18c);
 
 enum spi_xfer_mode {
 	XFER_MODE_NONE = 0,
diff --git a/src/soc/nvidia/tegra124/sysctr.h b/src/soc/nvidia/tegra124/sysctr.h
index 33f4e4bdce..1d7f53c3e1 100644
--- a/src/soc/nvidia/tegra124/sysctr.h
+++ b/src/soc/nvidia/tegra124/sysctr.h
@@ -50,5 +50,6 @@ struct sysctr_regs {
 	uint32_t counterid10;
 	uint32_t counterid11;
 };
+check_member(sysctr_regs, counterid11, 0xffc);
 
 #endif	/* __SOC_NVIDIA_TEGRA124_SYSCTR_H__ */