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authorElyes HAOUAS <ehaouas@noos.fr>2018-08-07 12:14:33 +0200
committerMartin Roth <martinroth@google.com>2018-08-09 15:49:53 +0000
commit809aeeed98104c016a5ee1cdd5009a84a5611d8e (patch)
treecba013b306c1e18d219f79db9b0c77799fd832b0 /src/soc/nvidia/tegra124
parent6de6571f1c362c43dbfd04c79d1ddedcb953c724 (diff)
downloadcoreboot-809aeeed98104c016a5ee1cdd5009a84a5611d8e.tar.xz
src/soc: Fix typo
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra124')
-rw-r--r--src/soc/nvidia/tegra124/chip.h2
-rw-r--r--src/soc/nvidia/tegra124/sdram_lp0.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h
index 6994ca2210..d9ab67bf5f 100644
--- a/src/soc/nvidia/tegra124/chip.h
+++ b/src/soc/nvidia/tegra124/chip.h
@@ -88,7 +88,7 @@ struct soc_nvidia_tegra124_config {
int pixel_clock;
- /* The minimum link configuraton settings */
+ /* The minimum link configuration settings */
u32 lane_count;
u32 enhanced_framing;
u32 link_bw;
diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c
index d5019d9ef8..536ad31804 100644
--- a/src/soc/nvidia/tegra124/sdram_lp0.c
+++ b/src/soc/nvidia/tegra124/sdram_lp0.c
@@ -23,7 +23,7 @@
#include <stdlib.h>
/*
- * This function reads SDRAM parameters (and a few CLK_RST regsiter values) from
+ * This function reads SDRAM parameters (and a few CLK_RST register values) from
* the common BCT format and writes them into PMC scratch registers (where the
* BootROM expects them on LP0 resume). Since those store the same values in a
* different format, we follow a "translation table" taken from Nvidia's U-Boot