diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2016-05-20 14:50:38 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 18:27:39 +0200 |
| commit | 9071670a84281979709191307dc11f1350f81bd8 (patch) | |
| tree | abbe2589ab60851ca38b267ff065f73e8b0c26ec /src/soc/nvidia/tegra124 | |
| parent | 08492f70b79bbda54e6765949e7ee9aa98344b71 (diff) | |
| download | coreboot-9071670a84281979709191307dc11f1350f81bd8.tar.xz | |
nvidia/tegra124: Adjust memlayout to Chrome OS toolchain
The bootblock gets slightly too big, so adjust the space assigned to
it.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
BUG=none
BRANCH=none
TEST=emerge-nyan coreboot works again.
Change-Id: Ib44d98692ae88c7cd3610c8e643d7d48ac858161
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4b9038b018ed7a26fbce01d982b22166b328de37
Original-Change-Id: If494e49fb60c11e01ca780c84036ebf24459628c
Original-Reviewed-on: https://chromium-review.googlesource.com/346492
Original-Reviewed-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Queue: Stefan Reinauer <reinauer@google.com>
Original-Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://review.coreboot.org/15950
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/nvidia/tegra124')
| -rw-r--r-- | src/soc/nvidia/tegra124/include/soc/memlayout.ld | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 5bab362396..6e596f35a7 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -31,9 +31,9 @@ SECTIONS PRERAM_CBFS_CACHE(0x40006000, 16K) VBOOT2_WORK(0x4000A000, 16K) STACK(0x4000E000, 8K) - BOOTBLOCK(0x40010000, 24K) - VERSTAGE(0x40016000, 72K) - ROMSTAGE(0x40028000, 95K) + BOOTBLOCK(0x40010000, 26K) + VERSTAGE(0x40016800, 72K) + ROMSTAGE(0x40028800, 93K) TIMESTAMP(0x4003FC00, 1K) SRAM_END(0x40040000) |