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authorArthur Heymans <arthur@aheymans.xyz>2019-10-20 01:00:57 +0200
committerArthur Heymans <arthur@aheymans.xyz>2019-11-03 11:19:04 +0000
commit2f389f151a0db244def706bc90fd17fe091d8537 (patch)
tree4269a24bc3f25749c85eb39357d68135964e35ef /src/soc/nvidia/tegra124
parent7c9a0e8a9cfa90f8f413f3b485f8103bca80fac6 (diff)
downloadcoreboot-2f389f151a0db244def706bc90fd17fe091d8537.tar.xz
arch/arm: Pass cbmem_top to ramstage via calling argument
This solution is very generic and can in principle be implemented on all arch/soc. Instead trying to figure out which files can be removed from stages and which cbmem_top implementations need with preprocessor, rename all cbmem_top implementation to cbmem_top_romstage. Mechanisms set in place to pass on information from rom- to ram-stage will be placed in a followup commit. Change-Id: If31f0f1de17ffc92c9397f32b26db25aff4b7cab Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/nvidia/tegra124')
-rw-r--r--src/soc/nvidia/tegra124/Makefile.inc1
-rw-r--r--src/soc/nvidia/tegra124/verstage.c2
2 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index fb5389fa2f..e80125e953 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -46,7 +46,6 @@ romstage-y += ../tegra/pinmux.c
romstage-y += cache.c
romstage-y += uart.c
-ramstage-y += cbmem.c
ramstage-y += clock.c
ramstage-y += display.c
ramstage-y += dma.c
diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c
index 2495351f6c..7ecf31a84e 100644
--- a/src/soc/nvidia/tegra124/verstage.c
+++ b/src/soc/nvidia/tegra124/verstage.c
@@ -45,7 +45,7 @@ void verstage_mainboard_init(void)
early_mainboard_init();
}
-void stage_entry(void)
+void stage_entry(uintptr_t unused)
{
asm volatile ("bl arm_init_caches"
: : : "r0", "r1", "r2", "r3", "r4", "r5", "ip");