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| author | Julius Werner <jwerner@chromium.org> | 2019-02-20 18:39:22 -0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2019-02-22 06:44:02 +0000 |
| commit | 7e0dea6317dc74f8aba8c91d0f8e8a7237261c49 (patch) | |
| tree | c9f476b75f0f9fcfe84aeb00b396723b3bcf7f5b /src/soc/nvidia/tegra124 | |
| parent | 314b5c370b4655bc701985ddf1d1d478067e7baa (diff) | |
| download | coreboot-7e0dea6317dc74f8aba8c91d0f8e8a7237261c49.tar.xz | |
symbols.h: Add macro to define memlayout region symbols
When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.
This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).
Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.
Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/nvidia/tegra124')
| -rw-r--r-- | src/soc/nvidia/tegra124/verstage.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index d99f1a719e..2495351f6c 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -30,7 +30,8 @@ static void enable_cache(void) /* Whole space is uncached. */ mmu_config_range(0, 4096, DCACHE_OFF); /* SRAM is cached. MMU code will round size up to page size. */ - mmu_config_range((uintptr_t)_sram/MiB, DIV_ROUND_UP(_sram_size, MiB), + mmu_config_range((uintptr_t)_sram/MiB, + DIV_ROUND_UP(REGION_SIZE(sram), MiB), DCACHE_WRITEBACK); mmu_disable_range(0, 1); dcache_mmu_enable(); |