diff options
author | Aaron Durbin <adurbin@chromium.org> | 2015-05-15 13:15:34 -0500 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2015-05-26 22:32:47 +0200 |
commit | c6588c5af94e568bddd8111c3fca736f464042cf (patch) | |
tree | 0efa16d6948cfde369932fd18dec46102f807c2f /src/soc/nvidia/tegra132/Makefile.inc | |
parent | def0fb57dfd91e6599c622a7b2769164a5c02ef0 (diff) | |
download | coreboot-c6588c5af94e568bddd8111c3fca736f464042cf.tar.xz |
coreboot: introduce boot_device
The boot_device is a region_device that represents the
device from which coreboot retrieves and boots its stages.
The existing cbfs implementations use the boot_device as
the intermediary for accessing the CBFS region. Also,
there's currently only support for a read-only view of
the boot_device. i.e. one cannot write to the boot_device
using this view. However, a writable boot_device could
be added in the future.
Change-Id: Ic0da796ab161b8025c90631be3423ba6473ad31c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10216
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra132/Makefile.inc')
-rw-r--r-- | src/soc/nvidia/tegra132/Makefile.inc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 365dab314f..c192055cdf 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -2,7 +2,6 @@ ifeq ($(CONFIG_SOC_NVIDIA_TEGRA132),y) bootblock-y += bootblock.c bootblock-y += bootblock_asm.S -bootblock-y += cbfs.c bootblock-y += clock.c bootblock-y += spi.c bootblock-y += i2c.c @@ -23,7 +22,6 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif verstage-y += verstage.c -verstage-y += cbfs.c verstage-y += dma.c verstage-y += monotonic_timer.c verstage-y += spi.c @@ -39,7 +37,6 @@ verstage-y += i2c.c romstage-y += 32bit_reset.S romstage-y += romstage_asm.S romstage-y += addressmap.c -romstage-y += cbfs.c romstage-y += cbmem.c romstage-y += ccplex.c romstage-y += clock.c @@ -63,7 +60,6 @@ romstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += 32bit_reset.S ramstage-y += addressmap.c -ramstage-y += cbfs.c ramstage-y += cbmem.c ramstage-y += cpu.c ramstage-y += cpu_lib.S |