arm(64): Globally replace writel(v, a) with write32(a, v)

This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 7 insertions, 7 deletions

diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index 1cc59add84..f9356a91bc 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -46,12 +46,12 @@ static int ccplex_start(void)
 	struct tegra_pmc_regs * const pmc = PMC_REGS;
 
 	/* Set the handshake bit to be knocked down. */
-	writel(handshake_mask, &pmc->scratch118);
+	write32(&pmc->scratch118, handshake_mask);
 
 	/* Assert nCXRSET[1] */
 	reg = read32(CLK_RST_REG(rst_cpu_cmplx_set));
 	reg |= cxreset1_mask;
-	writel(reg, CLK_RST_REG(rst_cpu_cmplx_set));
+	write32(CLK_RST_REG(rst_cpu_cmplx_set), reg);
 
 	stopwatch_init_msecs_expire(&sw, timeout_ms);
 	while (1) {
@@ -140,14 +140,14 @@ static void request_ram_repair(void)
 	/* Perform cluster 0 ram repair */
 	reg = read32(&flow->ram_repair);
 	reg |= req;
-	writel(reg, &flow->ram_repair);
+	write32(&flow->ram_repair, reg);
 	while ((read32(&flow->ram_repair) & sts) != sts)
 		;
 
 	/* Perform cluster 1 ram repair */
 	reg = read32(&flow->ram_repair_cluster1);
 	reg |= req;
-	writel(reg, &flow->ram_repair_cluster1);
+	write32(&flow->ram_repair_cluster1, reg);
 	while ((read32(&flow->ram_repair_cluster1) & sts) != sts)
 		;
 
@@ -169,11 +169,11 @@ void ccplex_cpu_prepare(void)
 static void start_common_clocks(void)
 {
 	/* Clear fast CPU partition reset. */
-	writel(CRC_RST_CPUG_CLR_NONCPU, CLK_RST_REG(rst_cpug_cmplx_clr));
+	write32(CLK_RST_REG(rst_cpug_cmplx_clr), CRC_RST_CPUG_CLR_NONCPU);
 
 	/* Clear reset of L2 and CoreSight components. */
-	writel(CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
-	       CLK_RST_REG(rst_cpug_cmplx_clr));
+	write32(CLK_RST_REG(rst_cpug_cmplx_clr),
+		CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG);
 }
 
 void ccplex_cpu_start(void *entry_addr)