diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-09-20 15:07:52 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-28 08:44:55 +0100 |
| commit | 68a672c2c268295136e1ca186cab390494088490 (patch) | |
| tree | ba8afb65f303196b2cefc1640695c0feb371393c /src/soc/nvidia/tegra132/clk_rst.h | |
| parent | cd72103021a318741cd6bb51efe585ef09f0ce2b (diff) | |
| download | coreboot-68a672c2c268295136e1ca186cab390494088490.tar.xz | |
tegra132: Clean up clock register writes
Clean up functions to write to clk_enb and rst_dev registers and add
clock_disable and clock_set_reset functions to provide a complete API for
updating the registers.
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on ryu. Compiles
successfully on rush
Change-Id: Ib0b7e3fc322f18be396ecf3b02b2399d4ba33e9b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1bb222adc22c7e26077dfb2ba6e4d41a4965d183
Original-Change-Id: Icb8081fe3d80174c920eaaecf5cbb0aa912d5b19
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219191
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9099
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/nvidia/tegra132/clk_rst.h')
| -rw-r--r-- | src/soc/nvidia/tegra132/clk_rst.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra132/clk_rst.h b/src/soc/nvidia/tegra132/clk_rst.h index 485910586a..bde2b56fd3 100644 --- a/src/soc/nvidia/tegra132/clk_rst.h +++ b/src/soc/nvidia/tegra132/clk_rst.h @@ -151,7 +151,7 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr { u32 clk_enb_h_set; /* _CLK_ENB_H_SET 0x328 */ u32 clk_enb_h_clr; /* _CLK_ENB_H_CLR 0x32c */ u32 clk_enb_u_set; /* _CLK_ENB_U_SET 0x330 */ - u32 clk_enb_u_clk; /* _CLK_ENB_U_CLR 0x334 */ + u32 clk_enb_u_clr; /* _CLK_ENB_U_CLR 0x334 */ u32 _rsv22; /* 0x338 */ u32 ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD, 0x33c */ u32 rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET, 0x340 */ @@ -301,6 +301,12 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr { }; check_member(clk_rst_ctlr, clk_src_i2c6, 0x65C); +#define CLK_RST_REG(field_) \ + (&(((struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE)->field_)) + +/* L, H, U, V, W, X */ +#define DEV_CONFIG_BLOCKS 6 + #define TEGRA_DEV_L 0 #define TEGRA_DEV_H 1 #define TEGRA_DEV_U 2 |