diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-29 18:31:16 +0200 |
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committer | Martin Roth <martinroth@google.com> | 2016-07-31 19:27:53 +0200 |
commit | 038e7247dc9705ff2d47dd90ec9a807f6feb52ba (patch) | |
tree | 8cca6a6db31d20a8e045ee5892e8f9cb8de43f8d /src/soc/nvidia/tegra132/clock.c | |
parent | f9e7d1b0ca7282a0d51313a68f90e9298c0c46c6 (diff) | |
download | coreboot-038e7247dc9705ff2d47dd90ec9a807f6feb52ba.tar.xz |
src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra132/clock.c')
-rw-r--r-- | src/soc/nvidia/tegra132/clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c index 0db120d8d2..be12b856b1 100644 --- a/src/soc/nvidia/tegra132/clock.c +++ b/src/soc/nvidia/tegra132/clock.c @@ -508,7 +508,7 @@ void clock_cpu0_config(void) /* wait and try again */ if (timeout >= CLK_SWITCH_TIMEOUT_US) { printk(BIOS_ERR, "%s: PLLX programming timeout. " - "Switching cpu clock has falied.\n", + "Switching CPU clock has falied.\n", __func__); break; } |