diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-09-20 15:07:52 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-28 08:44:55 +0100 |
| commit | 68a672c2c268295136e1ca186cab390494088490 (patch) | |
| tree | ba8afb65f303196b2cefc1640695c0feb371393c /src/soc/nvidia/tegra132/i2c6.c | |
| parent | cd72103021a318741cd6bb51efe585ef09f0ce2b (diff) | |
| download | coreboot-68a672c2c268295136e1ca186cab390494088490.tar.xz | |
tegra132: Clean up clock register writes
Clean up functions to write to clk_enb and rst_dev registers and add
clock_disable and clock_set_reset functions to provide a complete API for
updating the registers.
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt on ryu. Compiles
successfully on rush
Change-Id: Ib0b7e3fc322f18be396ecf3b02b2399d4ba33e9b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1bb222adc22c7e26077dfb2ba6e4d41a4965d183
Original-Change-Id: Icb8081fe3d80174c920eaaecf5cbb0aa912d5b19
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/219191
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9099
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/nvidia/tegra132/i2c6.c')
| -rw-r--r-- | src/soc/nvidia/tegra132/i2c6.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/src/soc/nvidia/tegra132/i2c6.c b/src/soc/nvidia/tegra132/i2c6.c index af015057b3..887e2bb4b5 100644 --- a/src/soc/nvidia/tegra132/i2c6.c +++ b/src/soc/nvidia/tegra132/i2c6.c @@ -53,8 +53,7 @@ static void remove_clamps(int id) static void enable_sor_periph_clocks(void) { - setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_HOST1X); - setbits_le32(&clk_rst->clk_out_enb_x, CLK_X_DPAUX); + clock_enable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX); /* Give clocks time to stabilize. */ udelay(IO_STABILIZATION_DELAY); @@ -62,8 +61,7 @@ static void enable_sor_periph_clocks(void) static void disable_sor_periph_clocks(void) { - clrbits_le32(&clk_rst->clk_out_enb_l, CLK_L_HOST1X); - clrbits_le32(&clk_rst->clk_out_enb_x, CLK_X_DPAUX); + clock_disable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX); /* Give clocks time to stabilize. */ udelay(IO_STABILIZATION_DELAY); @@ -71,8 +69,7 @@ static void disable_sor_periph_clocks(void) static void unreset_sor_periphs(void) { - clrbits_le32(&clk_rst->rst_dev_l, CLK_L_HOST1X); - clrbits_le32(&clk_rst->rst_dev_x, CLK_X_DPAUX); + clock_clr_reset(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX); } void soc_configure_i2c6pad(void) @@ -108,5 +105,5 @@ void soc_configure_i2c6pad(void) /* Stop Host1X/DPAUX clocks and reset Host1X */ disable_sor_periph_clocks(); - setbits_le32(&clk_rst->rst_dev_l, CLK_L_HOST1X); + clock_set_reset_l(CLK_L_HOST1X); } |