diff options
author | Aaron Durbin <adurbin@chromium.org> | 2014-08-12 17:50:53 -0500 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-26 00:30:53 +0100 |
commit | 0e99044aabcca418bba48e2b1d93d0e4e4a38b47 (patch) | |
tree | a192e78ac2313a122cee086a5d24c99d891464f1 /src/soc/nvidia/tegra132/mmu_operations.c | |
parent | e8ab775c811365fe984d90489ed605e6a17f2f19 (diff) | |
download | coreboot-0e99044aabcca418bba48e2b1d93d0e4e4a38b47.tar.xz |
tegra132: allow mainboards to insert memory regions in address map
Depending on the needs of the mainboard certain regions of the address
map may need to be adjusted. Allow for that.
BUG=chrome-os-partner:31293
BRANCH=None
TEST=With ryu patches able to insert a non-cacheable memory region.
Change-Id: I68ead4a0f29da9a48d6d975cd41e2969db43ca55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88342562885b09c4350ba1c846b725b5f12c63d9
Original-Change-Id: Iaa657bba98d36a60f2c1a5dfbb8ded4e3a53476f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212161
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/mmu_operations.c')
-rw-r--r-- | src/soc/nvidia/tegra132/mmu_operations.c | 31 |
1 files changed, 18 insertions, 13 deletions
diff --git a/src/soc/nvidia/tegra132/mmu_operations.c b/src/soc/nvidia/tegra132/mmu_operations.c index 15147809b5..2c54d7ff01 100644 --- a/src/soc/nvidia/tegra132/mmu_operations.c +++ b/src/soc/nvidia/tegra132/mmu_operations.c @@ -44,39 +44,44 @@ static void print_memranges(struct memranges *mmap_ranges) } -static void tegra132_memrange_init(void) +static void tegra132_memrange_init(struct memranges *map) { uint64_t start,end; + const unsigned long devmem = MA_DEV | MA_NS | MA_RW; + const unsigned long cachedmem = MA_MEM | MA_NS | MA_RW; - memranges_init_empty(&t132_mmap_ranges); + memranges_init_empty(map); memory_in_range_below_4gb(&start,&end); /* Device memory below DRAM */ - memranges_insert(&t132_mmap_ranges, 0, start * MiB, MA_DEV | MA_NS | - MA_RW); + memranges_insert(map, 0, start * MiB, devmem); /* DRAM */ - memranges_insert(&t132_mmap_ranges, start * MiB, (end-start) * MiB, - MA_MEM | MA_NS | MA_RW); + memranges_insert(map, start * MiB, (end-start) * MiB, cachedmem); memory_in_range_above_4gb(&start,&end); - memranges_insert(&t132_mmap_ranges, start * MiB, (end-start) * MiB, - MA_MEM | MA_NS | MA_RW); + memranges_insert(map, start * MiB, (end-start) * MiB, cachedmem); /* SRAM */ - memranges_insert(&t132_mmap_ranges, TEGRA_SRAM_BASE, TEGRA_SRAM_SIZE, - MA_MEM | MA_NS | MA_RW); + memranges_insert(map, TEGRA_SRAM_BASE, TEGRA_SRAM_SIZE, cachedmem); +} - print_memranges(&t132_mmap_ranges); +void __attribute__((weak)) mainboard_add_memory_ranges(struct memranges *map) +{ + /* Don't add any ranges by default. */ } void tegra132_mmu_init(void) { uint64_t *ttb_buffer = (uint64_t*)CONFIG_TTB_BUFFER; uint64_t ttb_size = (uint64_t)CONFIG_TTB_SIZE; - tegra132_memrange_init(); - mmu_init(&t132_mmap_ranges,ttb_buffer,ttb_size); + struct memranges *map = &t132_mmap_ranges; + + tegra132_memrange_init(map); + mainboard_add_memory_ranges(map); + print_memranges(map); + mmu_init(map,ttb_buffer,ttb_size); mmu_enable((uint64_t)ttb_buffer); } |