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| author | Aaron Durbin <adurbin@chromium.org> | 2014-08-27 16:58:42 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-27 08:04:11 +0100 |
| commit | 97b78cba5afd1636a306cc6533f8abd0a886483a (patch) | |
| tree | 61c075174b739137b89c68060a509c4d330a54a9 /src/soc/nvidia/tegra132/power.h | |
| parent | cc175767c98b60a7a9be4651a5187d79b40164c1 (diff) | |
| download | coreboot-97b78cba5afd1636a306cc6533f8abd0a886483a.tar.xz | |
tegra132: support GIC secondary cpu support
For the secondary CPUs the set of banked registers needs to be
initialized. In the boot CPU path all both the CPU's banked
registers and the global register set is initialized.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu in kernel.
Change-Id: I3a7bc708f726c4435afca817a251790f536844d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 813b0a8b3faacf2342164d385e5837ebede29b18
Original-Change-Id: Ie5db56ca052eebac4ed1a34eaeeb6bbd8a26ca30
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214774
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9018
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/power.h')
0 files changed, 0 insertions, 0 deletions