diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-11-25 16:47:56 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 20:46:16 +0200 |
| commit | d8060904eea998136f39866d0eaba233882a5f3f (patch) | |
| tree | 1d4abd1328ae75dd8cb32e6f194e35cce53e5d8e /src/soc/nvidia/tegra132/psci.c | |
| parent | e37c18f891920be529b90eda856cf7389f2c8bc3 (diff) | |
| download | coreboot-d8060904eea998136f39866d0eaba233882a5f3f.tar.xz | |
tegra132: prepare cpu startup in psci
In order to start CPUs while in secmon/psci one needs to
set up the proper SoC state. Therefore, refactor the current
CPU startup API to allow for this by adding cpu_prepare_startup()
and start_cpu_silent().
BUG=chrome-os-partner:32136
BRANCH=None
TEST=Built and booted kernel.
Change-Id: I1424500f6c9398f7d44350949c25bb3d4832cec7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 70f9cf67085b345b529b41dd6554e37d38a5b350
Original-Change-Id: I842a391d3e27ddbfcdef1a2d60e3c66e60f99c77
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/231936
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9531
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/psci.c')
| -rw-r--r-- | src/soc/nvidia/tegra132/psci.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/psci.c b/src/soc/nvidia/tegra132/psci.c index 0b5d793aaf..b075ffc353 100644 --- a/src/soc/nvidia/tegra132/psci.c +++ b/src/soc/nvidia/tegra132/psci.c @@ -18,9 +18,21 @@ */ #include <arch/psci.h> +#include <soc/cpu.h> + +static void *cpu_on_entry_point; void psci_soc_init(uintptr_t cpu_on_entry) { + /* + * Stash secmon entry point for CPUs starting up. The 32-bit reset + * vector register is accessible in < EL3 so one has to attempt to + * plug the potential race for that register being changed out from + * under us. Therefore, we set the appropriate registers here, but + * it is also done on each CPU_ON request. + */ + cpu_on_entry_point = (void *)cpu_on_entry; + cpu_prepare_startup(cpu_on_entry_point); } static size_t children_at_level(int parent_level, uint64_t mpidr) |