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| author | Jimmy Zhang <jimmzhang@nvidia.com> | 2014-07-23 17:42:45 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-17 16:39:22 +0100 |
| commit | aa228d08e9b67bd36dd9952e9e0eadc8dbe3a8d9 (patch) | |
| tree | 368360d13457e26490dd4895c7dbf22cb617b484 /src/soc/nvidia/tegra132/ramstage.c | |
| parent | 6ad6e3d84ab65357ce0cc64ad6ecff1cbd3fcd2c (diff) | |
| download | coreboot-aa228d08e9b67bd36dd9952e9e0eadc8dbe3a8d9.tar.xz | |
Tegra132: Configure CPU clock
Since CCLK_BURST_POLICY and SUPER_CCLK_DIVIDER are not accesible
from AVP, the first place that can change CPU clock is after CPU
has been brought up, ie, ramstage in this case.
CPU initial clock source is set to PLLP by MTS.
BUG=None
TEST=Norrin64 and A44
Original-Change-Id: I525bb2fa2be0afba52837bc0178950541535fd22
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209698
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ba77e26508bb4a50a08d07ad15632ff1ba501bfa)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icf2458c491b4b3a553d3e01f88c6f25b25639e89
Reviewed-on: http://review.coreboot.org/8677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/ramstage.c')
| -rw-r--r-- | src/soc/nvidia/tegra132/ramstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c index b3b4db2c86..40d80ff8b8 100644 --- a/src/soc/nvidia/tegra132/ramstage.c +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -20,10 +20,13 @@ #include <arch/stages.h> #include <soc/addressmap.h> #include "mmu_operations.h" +#include <soc/clock.h> void arm64_soc_init(void) { trustzone_region_init(); tegra132_mmu_init(); + + clock_cpu0_config(); } |