diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-07-17 11:42:35 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-13 00:12:23 +0100 |
| commit | da9b9f324b7c4aea46c55bdbd1365a018791ee18 (patch) | |
| tree | 8e2462a737133a65ce483702eadeecba7bd1e0b7 /src/soc/nvidia/tegra132/ramstage.c | |
| parent | 2486957514ab722aa1a129e306ac0180ed864112 (diff) | |
| download | coreboot-da9b9f324b7c4aea46c55bdbd1365a018791ee18.tar.xz | |
t132: Add mmu support
Add support for mmu initialization and enabling caches. mmu_operations provides
functions to add mmap_regions using memrange library and then calls mmu_init for
armv8.
BUG=chrome-os-partner:30688
BRANCH=None
TEST=Compiles rush successfully and boots until depthcharge load. Goes past
all the earlier alignment errors.
Original-Change-Id: I57c2be80427fa77239093c79ece73e31fd319239
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208762
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit a6141d13d40cfa5a493bde44e69c588dda97e8fd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I33bf4b2e28b85a3117b566cb8497f2bd5aabb69b
Reviewed-on: http://review.coreboot.org/8647
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra132/ramstage.c')
| -rw-r--r-- | src/soc/nvidia/tegra132/ramstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/ramstage.c b/src/soc/nvidia/tegra132/ramstage.c index 8d64c3e11f..ad553d43cc 100644 --- a/src/soc/nvidia/tegra132/ramstage.c +++ b/src/soc/nvidia/tegra132/ramstage.c @@ -21,6 +21,7 @@ #include <arch/stages.h> #include <soc/addressmap.h> #include "mc.h" +#include "mmu_operations.h" void arm64_soc_init(void) { @@ -44,4 +45,6 @@ void arm64_soc_init(void) end -= tz_size_mib; write32(end << 20, &mc->security_cfg0); write32(tz_size_mib, &mc->security_cfg1); + + tegra132_mmu_init(); } |