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authorJimmy Zhang <jimmzhang@nvidia.com>2015-01-06 13:42:26 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-14 09:04:29 +0200
commitd046fe86d8388b1a792538dfc9eda627885cb12b (patch)
tree6f8a44b1d33bab41fc7e24f8eaf697c2ee3f020b /src/soc/nvidia/tegra132
parentcfc0cff14b51f06980362ecb15466c7f539c99d2 (diff)
downloadcoreboot-d046fe86d8388b1a792538dfc9eda627885cb12b.tar.xz
rush: Configure display related clock, pad, and power
BUG=chrome-os-partner:34336 BRANCH=none TEST=build rush Change-Id: I9c2235ccc5571f1919dc013c62488390fe31dcbc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7468c14842c680be81620ad3fd2ea9ae056d525f Original-Change-Id: Iaf7f70727fc914b9bb2d063c9a30ece4451d40da Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/238942 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9613 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132')
-rw-r--r--src/soc/nvidia/tegra132/i2c6.c21
-rw-r--r--src/soc/nvidia/tegra132/include/soc/padconfig.h2
2 files changed, 14 insertions, 9 deletions
diff --git a/src/soc/nvidia/tegra132/i2c6.c b/src/soc/nvidia/tegra132/i2c6.c
index 86373d621e..73a98562ad 100644
--- a/src/soc/nvidia/tegra132/i2c6.c
+++ b/src/soc/nvidia/tegra132/i2c6.c
@@ -83,14 +83,7 @@ void soc_configure_i2c6pad(void)
* and put Host1X back in reset. DPAUX must remain out of
* reset and the SOR partition must remained unpowergated.
*/
- power_ungate_partition(POWER_PARTID_SOR);
-
- /* Host1X needs a valid clock source so DPAUX can be accessed */
- clock_configure_source(host1x, PLLP, 204000);
-
- enable_sor_periph_clocks();
- remove_clamps(POWER_PARTID_SOR);
- unreset_sor_periphs();
+ soc_configure_host1x();
/* Now we can write the I2C6 mux in DPAUX */
write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);
@@ -106,3 +99,15 @@ void soc_configure_i2c6pad(void)
disable_sor_periph_clocks();
clock_set_reset_l(CLK_L_HOST1X);
}
+
+void soc_configure_host1x(void)
+{
+ power_ungate_partition(POWER_PARTID_SOR);
+
+ /* Host1X needs a valid clock source so DPAUX can be accessed. */
+ clock_configure_source(host1x, PLLP, 204000);
+
+ enable_sor_periph_clocks();
+ remove_clamps(POWER_PARTID_SOR);
+ unreset_sor_periphs();
+}
diff --git a/src/soc/nvidia/tegra132/include/soc/padconfig.h b/src/soc/nvidia/tegra132/include/soc/padconfig.h
index 569fe4624c..843b4ee1cd 100644
--- a/src/soc/nvidia/tegra132/include/soc/padconfig.h
+++ b/src/soc/nvidia/tegra132/include/soc/padconfig.h
@@ -87,5 +87,5 @@ struct pad_config {
void soc_configure_pads(const struct pad_config * const entries, size_t num);
/* I2C6 requires special init as its pad lives int the SOR/DPAUX block */
void soc_configure_i2c6pad(void);
-
+void soc_configure_host1x(void);
#endif /* __SOC_NVIDIA_TEGRA132_PAD_CFG_H */