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authorYen Lin <yelin@nvidia.com>2015-01-07 17:04:15 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-13 12:19:33 +0200
commit9b99d7b435f24a2e3a70c6b29a4dba13efc3ef47 (patch)
tree927ed1d5faf130a68353735290cb54c90bb49fc1 /src/soc/nvidia/tegra132
parentafe9c8a03bdd682dc160d7c33102159c5aef5247 (diff)
downloadcoreboot-9b99d7b435f24a2e3a70c6b29a4dba13efc3ef47.tar.xz
t132: add RAM repair to cluster 1
RAM repair has to be performed to cluster 1 also. BRANCH=none BUG=none TEST=Test on Rush and make sure RAM repair completes Change-Id: I0daf969a995a2be152270bc06501eaf086a13a97 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 6b07894cc737cb192f68e254d522b55d8ca3b2f3 Original-Change-Id: I458e0a66d76318c6a4aa82547c9037c7b969f1e1 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/239360 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9592 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra132')
-rw-r--r--src/soc/nvidia/tegra132/ccplex.c12
-rw-r--r--src/soc/nvidia/tegra132/include/soc/flow.h8
2 files changed, 17 insertions, 3 deletions
diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c
index ea92b31324..520c244fbf 100644
--- a/src/soc/nvidia/tegra132/ccplex.c
+++ b/src/soc/nvidia/tegra132/ccplex.c
@@ -135,14 +135,22 @@ static void request_ram_repair(void)
printk(BIOS_DEBUG, "Requesting RAM repair.\n");
+ stopwatch_init(&sw);
+
+ /* Perform cluster 0 ram repair */
reg = read32(&flow->ram_repair);
reg |= req;
write32(reg, &flow->ram_repair);
-
- stopwatch_init(&sw);
while ((read32(&flow->ram_repair) & sts) != sts)
;
+ /* Perform cluster 1 ram repair */
+ reg = read32(&flow->ram_repair_cluster1);
+ reg |= req;
+ write32(reg, &flow->ram_repair_cluster1);
+ while ((read32(&flow->ram_repair_cluster1) & sts) != sts)
+ ;
+
printk(BIOS_DEBUG, "RAM repair complete in %ld usecs.\n",
stopwatch_duration_usecs(&sw));
}
diff --git a/src/soc/nvidia/tegra132/include/soc/flow.h b/src/soc/nvidia/tegra132/include/soc/flow.h
index 01dbc14208..e0cf495651 100644
--- a/src/soc/nvidia/tegra132/include/soc/flow.h
+++ b/src/soc/nvidia/tegra132/include/soc/flow.h
@@ -35,8 +35,14 @@ struct flow_ctlr {
u32 cpu_pwr_csr; /* offset 0x38 */
u32 mpid; /* offset 0x3c */
u32 ram_repair; /* offset 0x40 */
+ u32 flow_dbg_sel; /* offset 0x44 */
+ u32 flow_dbg_cnt0; /* offset 0x48 */
+ u32 flow_dbg_cnt1; /* offset 0x4c */
+ u32 flow_dbg_qual; /* offset 0x50 */
+ u32 flow_ctlr_spare; /* offset 0x54 */
+ u32 ram_repair_cluster1;/* offset 0x58 */
};
-check_member(flow_ctlr, ram_repair, 0x40);
+check_member(flow_ctlr, ram_repair_cluster1, 0x58);
enum {
FLOW_MODE_SHIFT = 29,