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authorPatrick Georgi <pgeorgi@chromium.org>2015-06-22 19:41:29 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-06-30 21:43:01 +0200
commit40a3e321d4e8f2877de1700db67b8c7f7ea89820 (patch)
treeb8270b2ceb9e290d2e4e9a99868acb9cd335de6f /src/soc/nvidia/tegra210/Kconfig
parent7f641e68f25c0b79960a97a6b265851c46298aae (diff)
downloadcoreboot-40a3e321d4e8f2877de1700db67b8c7f7ea89820.tar.xz
nvidia/tegra210: add new SoC
This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/Kconfig')
-rw-r--r--src/soc/nvidia/tegra210/Kconfig143
1 files changed, 143 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig
new file mode 100644
index 0000000000..257345e303
--- /dev/null
+++ b/src/soc/nvidia/tegra210/Kconfig
@@ -0,0 +1,143 @@
+config SOC_NVIDIA_TEGRA210
+ bool
+ default n
+ select ARCH_BOOTBLOCK_ARMV4
+ select ARCH_VERSTAGE_ARMV4
+ select ARCH_ROMSTAGE_ARMV4
+ select ARCH_RAMSTAGE_ARMV8_64
+ select ARCH_ARM64_CPU_CORTEX_A57
+ select ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT
+ select BOOTBLOCK_CONSOLE
+ select GIC
+ select HAVE_MONOTONIC_TIMER
+ select GENERIC_UDELAY
+ select HAVE_HARD_RESET
+ select HAVE_UART_SPECIAL
+ select HAVE_UART_MEMORY_MAPPED
+ select EARLY_CONSOLE
+ select ARM_BOOTBLOCK_CUSTOM
+ select DYNAMIC_CBMEM
+ select ARM64_USE_ARM_TRUSTED_FIRMWARE
+ select HAS_PRECBMEM_TIMESTAMP_REGION
+ select CHROMEOS_RAMOOPS_NON_ACPI
+ select GENERIC_GPIO_LIB
+
+if SOC_NVIDIA_TEGRA210
+
+config MAINBOARD_DO_DSI_INIT
+ bool "Use dsi graphics interface"
+ depends on MAINBOARD_DO_NATIVE_VGA_INIT
+ default n
+ help
+ Initialize dsi display
+
+config MAINBOARD_DO_SOR_INIT
+ bool "Use dp graphics interface"
+ depends on MAINBOARD_DO_NATIVE_VGA_INIT
+ default n
+ help
+ Initialize dp display
+
+config BOOTBLOCK_CPU_INIT
+ string
+ default "soc/nvidia/tegra210/bootblock.c"
+ help
+ CPU/SoC-specific bootblock code. This is useful if the
+ bootblock must load microcode or copy data from ROM before
+ searching for the bootblock.
+
+config MAX_CPUS
+ int
+ default 4
+
+choice CONSOLE_SERIAL_TEGRA210_UART_CHOICES
+ prompt "Serial Console UART"
+ default CONSOLE_SERIAL_TEGRA210_UARTA
+ depends on CONSOLE_SERIAL_UART
+
+config CONSOLE_SERIAL_TEGRA210_UARTA
+ bool "UARTA"
+ help
+ Serial console on UART A.
+
+config CONSOLE_SERIAL_TEGRA210_UARTB
+ bool "UARTB"
+ help
+ Serial console on UART B.
+
+config CONSOLE_SERIAL_TEGRA210_UARTC
+ bool "UARTC"
+ help
+ Serial console on UART C.
+
+config CONSOLE_SERIAL_TEGRA210_UARTD
+ bool "UARTD"
+ help
+ Serial console on UART D.
+
+config CONSOLE_SERIAL_TEGRA210_UARTE
+ bool "UARTE"
+ help
+ Serial console on UART E.
+
+endchoice
+
+config CONSOLE_SERIAL_TEGRA210_UART_ADDRESS
+ hex
+ depends on CONSOLE_SERIAL_UART
+ default 0x70006000 if CONSOLE_SERIAL_TEGRA210_UARTA
+ default 0x70006040 if CONSOLE_SERIAL_TEGRA210_UARTB
+ default 0x70006200 if CONSOLE_SERIAL_TEGRA210_UARTC
+ default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD
+ default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE
+ help
+ Map the UART names to the respective MMIO addres.
+
+config BOOTROM_SDRAM_INIT
+ bool "SoC BootROM does SDRAM init with full BCT"
+ default n
+ help
+ Use during Foster LPDDR4 bringup.
+
+config TRUSTZONE_CARVEOUT_SIZE_MB
+ hex "Size of Trust Zone region"
+ default 0x14
+ help
+ Size of Trust Zone area in MiB to reserve in memory map.
+
+# Default to 700MHz. This value is based on nv bootloader setting.
+config PLLX_KHZ
+ int
+ default 700000
+endif
+
+config HAVE_MTC
+ bool "Add external Memory controller Training Code binary"
+ default n
+ depends on USE_BLOBS
+ help
+ Select this option to add emc training firmware
+
+if HAVE_MTC
+
+config MTC_FILE
+ string "tegra mtc firmware filename"
+ default "tegra_mtc.bin"
+ help
+ The filename of the mtc firmware
+
+config MTC_DIRECTORY
+ string "Directory where MTC firmware file is located"
+ default "."
+ help
+ Path to directory where MTC firmware file is located.
+
+config MTC_ADDRESS
+ hex
+ default 0x81000000
+ help
+ The DRAM location where MTC firmware to be loaded in. This location
+ needs to be consistent with the location defined in tegra_mtc.ld
+
+endif # HAVE_MTC
+