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| author | Furquan Shaikh <furquan@google.com> | 2015-07-07 21:35:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-13 09:19:34 +0200 |
| commit | 3ae5044b7330ea4af0214b7db29749eed17f2e66 (patch) | |
| tree | b01c3bca82b607bf24ce4aee2fca29e6208d0c4f /src/soc/nvidia/tegra210/Makefile.inc | |
| parent | ccc55fdc6fae37a085e9f1a8a19a539728907ca1 (diff) | |
| download | coreboot-3ae5044b7330ea4af0214b7db29749eed17f2e66.tar.xz | |
t210: Add TZDRAM_BASE param to BL31_MAKEARGS
1. Make TTB_SIZE Kconfig option
2. Add Kconfig option for maximum secure component size
3. Add check in Makefile to ensure that Trustzone area is big enough
to hold TTB and secure components
4. Calculate TZDRAM_BASE depending upon TTB_SIZE and TZ_CARVEOUT_SIZE
BUG=chrome-os-partner:42319
BRANCH=None
Change-Id: I9ceb46ceedc931826657e5a0f6fc2b1886526bf8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a425d4978a467b157ea5d71e600242ebf427b5bb
Original-Change-Id: I152a38830773d85aafab49c92cef945b7c4eb62c
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284074
Original-Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/10878
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/Makefile.inc')
| -rw-r--r-- | src/soc/nvidia/tegra210/Makefile.inc | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/Makefile.inc b/src/soc/nvidia/tegra210/Makefile.inc index 98e752c1a3..3b2dc7c5b1 100644 --- a/src/soc/nvidia/tegra210/Makefile.inc +++ b/src/soc/nvidia/tegra210/Makefile.inc @@ -146,6 +146,28 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" $(CBOOTIMAGE) $(CBOOTIMAGE_OPTS) $(BCT_WRAPPER) $@ +# We need to ensure that TZ memory has enough space to hold TTB and resident EL3 +# components (including BL31 and Secure OS) +ttb_size=$(shell printf "%d" $(CONFIG_TTB_SIZE_MB)) +sec_size=$(shell printf "%d" $(CONFIG_SEC_COMPONENT_SIZE_MB)) +req_tz_size=$(shell expr $(ttb_size) + $(sec_size)) + +tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) + +ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1) + $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be atleast as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") +endif + +# BL31 component is placed towards the end of 32-bit address space. This assumes +# that TrustZone memory is placed at the end of 32-bit address space. Within the +# TZ memory, we place TTB at the beginning and then remaining space can be used +# up by BL31 and secure OS. Calculate TZDRAM_BASE i.e. base of BL31 component +# by: +# 0x1000 = end of 32-bit address space in MiB +# 0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) = start of TZ memory in MiB +# 0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB) +# = skip TTB buffer and get base address of BL31 +BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) + $(CONFIG_TTB_SIZE_MB)) << 20)) BL31_MAKEARGS += PLAT=tegra TARGET_SOC=t210 # MTC fw |