diff options
author | Patrick Georgi <pgeorgi@chromium.org> | 2015-06-22 19:41:29 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-30 21:43:01 +0200 |
commit | 40a3e321d4e8f2877de1700db67b8c7f7ea89820 (patch) | |
tree | b8270b2ceb9e290d2e4e9a99868acb9cd335de6f /src/soc/nvidia/tegra210/include | |
parent | 7f641e68f25c0b79960a97a6b265851c46298aae (diff) | |
download | coreboot-40a3e321d4e8f2877de1700db67b8c7f7ea89820.tar.xz |
nvidia/tegra210: add new SoC
This includes Chrome OS downstream up to Change-Id: Ic89ed54c.
Change-Id: I81853434600390d643160fe57554495b2bfe60ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10633
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/include')
37 files changed, 6755 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h new file mode 100644 index 0000000000..4a5372da75 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright 2014 Google Inc. + * + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ADDRESS_MAP_H__ +#define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ADDRESS_MAP_H__ + +#include <stddef.h> +#include <stdint.h> + +enum { + TEGRA_SRAM_BASE = 0x40000000, + TEGRA_SRAM_SIZE = 0x40000 +}; + +enum { + TEGRA_ARM_PERIPHBASE = 0x50040000, + TEGRA_GICD_BASE = 0x50041000, + TEGRA_GICC_BASE = 0x50042000, + TEGRA_ARM_DISPLAYA = 0x54200000, + TEGRA_ARM_DISPLAYB = 0x54240000, + TEGRA_DSIA_BASE = 0x54300000, + TEGRA_DSIB_BASE = 0x54400000, + TEGRA_ARM_SOR = 0x54540000, + TEGRA_ARM_DPAUX = 0x545c0000, + TEGRA_PG_UP_BASE = 0x60000000, + TEGRA_TMRUS_BASE = 0x60005010, + TEGRA_CLK_RST_BASE = 0x60006000, + TEGRA_FLOW_BASE = 0x60007000, + TEGRA_SB_BASE = 0x6000C200, + TEGRA_GPIO_BASE = 0x6000D000, + TEGRA_EVP_BASE = 0x6000F000, + TEGRA_APB_DMA_BASE = 0x60020000, + TEGRA_APB_MISC_BASE = 0x70000000, + TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800, + TEGRA_APB_PINGROUP_BASE = TEGRA_APB_MISC_BASE + 0x0868, + TEGRA_APB_PINMUX_BASE = TEGRA_APB_MISC_BASE + 0x3000, + TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000, + TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040, + TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200, + TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300, + TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400, + TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000, + TEGRA_PWM_BASE = TEGRA_APB_MISC_BASE + 0xA000, + TEGRA_I2C1_BASE = TEGRA_APB_MISC_BASE + 0xC000, + TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380, + TEGRA_I2C2_BASE = TEGRA_APB_MISC_BASE + 0xC400, + TEGRA_I2C3_BASE = TEGRA_APB_MISC_BASE + 0xC500, + TEGRA_I2C4_BASE = TEGRA_APB_MISC_BASE + 0xC700, + TEGRA_I2C5_BASE = TEGRA_APB_MISC_BASE + 0xD000, + TEGRA_I2C6_BASE = TEGRA_APB_MISC_BASE + 0xD100, + TEGRA_SPI1_BASE = TEGRA_APB_MISC_BASE + 0xD400, + TEGRA_SPI2_BASE = TEGRA_APB_MISC_BASE + 0xD600, + TEGRA_SPI3_BASE = TEGRA_APB_MISC_BASE + 0xD800, + TEGRA_SPI4_BASE = TEGRA_APB_MISC_BASE + 0xDA00, + TEGRA_SPI5_BASE = TEGRA_APB_MISC_BASE + 0xDC00, + TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, + TEGRA_SBC1_BASE = TEGRA_SPI1_BASE, + TEGRA_SBC2_BASE = TEGRA_SPI2_BASE, + TEGRA_SBC3_BASE = TEGRA_SPI3_BASE, + TEGRA_SBC4_BASE = TEGRA_SPI4_BASE, + TEGRA_SBC5_BASE = TEGRA_SPI5_BASE, + TEGRA_SBC6_BASE = TEGRA_SPI6_BASE, + TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400, + TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, + TEGRA_MC_BASE = 0x70019000, + TEGRA_EMC_BASE = 0x7001B000, + TEGRA_CLUSTER_CLOCK_BASE = 0x70040000, + TEGRA_QSPI_BASE = 0x70410000, + TEGRA_CSITE_BASE = 0x70800000, + TEGRA_SDMMC_BASE = 0x700b0000, + TEGRA_SDMMC1_BASE = TEGRA_SDMMC_BASE + 0x0000, + TEGRA_SDMMC2_BASE = TEGRA_SDMMC_BASE + 0x0200, + TEGRA_SDMMC3_BASE = TEGRA_SDMMC_BASE + 0x0400, + TEGRA_SDMMC4_BASE = TEGRA_SDMMC_BASE + 0x0600, + TEGRA_MIPI_CAL_BASE = 0x700E3000, + TEGRA_SYSCTR0_BASE = 0x700F0000, + TEGRA_I2S1_BASE = 0x70301100, + TEGRA_USBD_BASE = 0x7D000000, + TEGRA_USB2_BASE = 0x7D004000, + TEGRA_USB3_BASE = 0x7D008000, +}; + +enum { + TEGRA_I2C_BASE_COUNT = 6, +}; + +#define GPU_CARVEOUT_SIZE_MB 1 + +/* Return total size of DRAM memory configured on the platform. */ +int sdram_size_mb(void); + +/* Find memory below and above 4GiB boundary repsectively. All units 1MiB. */ +void memory_in_range_below_4gb(uintptr_t *base_mib, uintptr_t *end_mib); +void memory_in_range_above_4gb(uintptr_t *base_mib, uintptr_t *end_mib); + +enum { + CARVEOUT_TZ, + CARVEOUT_SEC, + CARVEOUT_MTS, + CARVEOUT_VPR, + CARVEOUT_GPU, + CARVEOUT_NUM, +}; + +/* Provided the careout id, obtain the base and size in 1MiB units. */ +void carveout_range(int id, uintptr_t *base_mib, size_t *size_mib); +void print_carveouts(void); + +/* + * Add any board-specific memory ranges to the address map when executing + * on aarchv8 core. + */ +struct memranges; +void mainboard_add_memory_ranges(struct memranges *map); + +/* + * There are complications accessing the Trust Zone carveout region. The + * AVP cannot access these registers and the CPU can't access this register + * as a non-secure access. When the page tables live in non-secure memory + * these registers cannot be accessed either. Thus, this function handles + * both the AVP case and non-secured access case by keeping global state. + */ +void trustzone_region_init(void); +void gpu_region_init(void); + +#endif /* __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/ccplex.h b/src/soc/nvidia/tegra210/include/soc/ccplex.h new file mode 100644 index 0000000000..d1aaa8bb2c --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/ccplex.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_CCPLEX_H__ +#define __SOC_NVIDIA_TEGRA210_CCPLEX_H__ + +#include <stdint.h> + +#define MTS_LOAD_ADDRESS 0x82000000 + +/* Prepare the clocks and rails to start the cpu. */ +void ccplex_cpu_prepare(void); + +/* Start cpu0 and have it start executing at entry_addr */ +void ccplex_cpu_start(void *entry_addr); + +#endif /* __SOC_NVIDIA_TEGRA210_CCPLEX_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/clk_rst.h b/src/soc/nvidia/tegra210/include/soc/clk_rst.h new file mode 100644 index 0000000000..60ee112d5e --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/clk_rst.h @@ -0,0 +1,607 @@ +/* + * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA210_CLK_RST_H_ +#define _TEGRA210_CLK_RST_H_ +#include <stdint.h> +#include <stddef.h> + +/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ +struct __attribute__ ((__packed__)) clk_rst_ctlr { + u32 rst_src; /* _RST_SOURCE, 0x000 */ + u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ + u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ + u32 rst_dev_u; /* _RST_DEVICES_U, 0x00c */ + u32 clk_out_enb_l; /* _CLK_OUT_ENB_L, 0x010 */ + u32 clk_out_enb_h; /* _CLK_OUT_ENB_H, 0x014 */ + u32 clk_out_enb_u; /* _CLK_OUT_ENB_U, 0x018 */ + u32 _rsv0; /* 0x01c */ + u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ + u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ + u32 sclk_brst_pol; /* _SCLK_BURST_POLICY, 0x028 */ + u32 super_sclk_div; /* _SUPER_SCLK_DIVIDER, 0x02C */ + u32 clk_sys_rate; /* _CLK_SYSTEM_RATE, 0x030 */ + u32 _rsv1[3]; /* 0x034-03c */ + u32 cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY, 0x040 */ + u32 clk_mask_arm; /* _CLK_MASK_ARM, 0x044 */ + u32 misc_clk_enb; /* _MISC_CLK_ENB, 0x048 */ + u32 clk_cpu_cmplx; /* _CLK_CPU_CMPLX, 0x04C */ + u32 osc_ctrl; /* _OSC_CTRL, 0x050 */ + u32 pll_lfsr; /* _PLL_LFSR, 0x054 */ + u32 osc_freq_det; /* _OSC_FREQ_DET, 0x058 */ + u32 osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS, 0x05C */ + u32 _rsv2[8]; /* 0x060-07C */ + u32 pllc_base; /* _PLLC_BASE, 0x080 */ + u32 pllc_out; /* _PLLC_OUT, 0x084 */ + u32 pllc_misc; /* _PLLC_MISC, 0x088 */ + u32 pllc_misc_1; /* _PLLC_MISC_1, 0x08c */ + u32 pllm_base; /* _PLLM_BASE, 0x090 */ + u32 pllm_out; /* _PLLM_OUT, 0x094 */ + u32 pllm_misc1; /* _PLLM_MISC1, 0x098 */ + u32 pllm_misc2; /* _PLLM_MISC2, 0x09c */ + u32 pllp_base; /* _PLLP_BASE, 0x0a0 */ + u32 pllp_outa; /* _PLLP_OUTA, 0x0a4 */ + u32 pllp_outb; /* _PLLP_OUTB, 0x0a8 */ + u32 pllp_misc; /* _PLLP_MISC, 0x0ac */ + u32 plla_base; /* _PLLA_BASE, 0x0b0 */ + u32 plla_out; /* _PLLA_OUT, 0x0b4 */ + u32 _rsv3; /* 0x0b8 */ + u32 plla_misc; /* _PLLA_MISC, 0x0bc */ + u32 pllu_base; /* _PLLU_BASE, 0x0c0 */ + u32 _rsv4[2]; /* 0x0c4-0c8 */ + u32 pllu_misc; /* _PLLU_MISC, 0x0cc */ + u32 plld_base; /* _PLLD_BASE, 0x0d0 */ + u32 _rsv5[1]; /* 0x0d4 */ + u32 plld_misc1; /* _PLLD_MISC1, 0x0d8 */ + u32 plld_misc; /* _PLLD_MISC, 0x0dc */ + u32 pllx_base; /* _PLLX_BASE, 0x0e0 */ + u32 pllx_misc; /* _PLLX_MISC, 0x0e4 */ + u32 plle_base; /* _PLLE_BASE, 0x0e8 */ + u32 plle_misc; /* _PLLE_MISC, 0x0ec */ + u32 plls_base; /* _PLLS_BASE, 0x0f0 */ + u32 plls_misc; /* _PLLS_MISC, 0x0f4 */ + u32 _rsv6[2]; /* 0x0f8-0fc */ + u32 clk_src_i2s1; /* _CLK_SOURCE_I2S1, 0x100 */ + u32 clk_src_i2s2; /* _CLK_SOURCE_I2S2, 0x104 */ + u32 clk_src_spdif_out; /* _CLK_SOURCE_SPDIF_OUT, 0x108 */ + u32 clk_src_spdif_in; /* _CLK_SOURCE_SPDIF_IN, 0x10c */ + u32 clk_src_pwm; /* _CLK_SOURCE_PWM, 0x110 */ + u32 _rsv7; /* 0x114 */ + u32 clk_src_sbc2; /* _CLK_SOURCE_SBC2, 0x118 */ + u32 clk_src_sbc3; /* _CLK_SOURCE_SBC3, 0x11c */ + u32 _rsv8; /* 0x120 */ + u32 clk_src_i2c1; /* _CLK_SOURCE_I2C1, 0x124 */ + u32 clk_src_i2c5; /* _CLK_SOURCE_I2C5, 0x128 */ + u32 _rsv9[2]; /* 0x12c-130 */ + u32 clk_src_sbc1; /* _CLK_SOURCE_SBC1, 0x134 */ + u32 clk_src_disp1; /* _CLK_SOURCE_DISP1, 0x138 */ + u32 clk_src_disp2; /* _CLK_SOURCE_DISP2, 0x13c */ + u32 _rsv10[2]; /* 0x140-144 */ + u32 clk_src_vi; /* _CLK_SOURCE_VI, 0x148 */ + u32 _rsv11; /* 0x14c */ + u32 clk_src_sdmmc1; /* _CLK_SOURCE_SDMMC1, 0x150 */ + u32 clk_src_sdmmc2; /* _CLK_SOURCE_SDMMC2, 0x154 */ + u32 clk_src_g3d; /* _CLK_SOURCE_G3D, 0x158 */ + u32 clk_src_g2d; /* _CLK_SOURCE_G2D, 0x15c */ + u32 clk_src_ndflash; /* _CLK_SOURCE_NDFLASH, 0x160 */ + u32 clk_src_sdmmc4; /* _CLK_SOURCE_SDMMC4, 0x164 */ + u32 clk_src_vfir; /* _CLK_SOURCE_VFIR, 0x168 */ + u32 clk_src_epp; /* _CLK_SOURCE_EPP, 0x16c */ + u32 clk_src_mpe; /* _CLK_SOURCE_MPE, 0x170 */ + u32 clk_src_hsi; /* _CLK_SOURCE_HSI, 0x174 */ + u32 clk_src_uarta; /* _CLK_SOURCE_UARTA, 0x178 */ + u32 clk_src_uartb; /* _CLK_SOURCE_UARTB, 0x17c */ + u32 clk_src_host1x; /* _CLK_SOURCE_HOST1X, 0x180 */ + u32 _rsv12[2]; /* 0x184-188 */ + u32 clk_src_hdmi; /* _CLK_SOURCE_HDMI, 0x18c */ + u32 _rsv13[2]; /* 0x190-194 */ + u32 clk_src_i2c2; /* _CLK_SOURCE_I2C2, 0x198 */ + u32 clk_src_emc; /* _CLK_SOURCE_EMC, 0x19c */ + u32 clk_src_uartc; /* _CLK_SOURCE_UARTC, 0x1a0 */ + u32 _rsv14; /* 0x1a4 */ + u32 clk_src_vi_sensor; /* _CLK_SOURCE_VI_SENSOR, 0x1a8 */ + u32 _rsv15[2]; /* 0x1ac-1b0 */ + u32 clk_src_sbc4; /* _CLK_SOURCE_SBC4, 0x1b4 */ + u32 clk_src_i2c3; /* _CLK_SOURCE_I2C3, 0x1b8 */ + u32 clk_src_sdmmc3; /* _CLK_SOURCE_SDMMC3, 0x1bc */ + u32 clk_src_uartd; /* _CLK_SOURCE_UARTD, 0x1c0 */ + u32 clk_src_uarte; /* _CLK_SOURCE_UARTE, 0x1c4 */ + u32 clk_src_vde; /* _CLK_SOURCE_VDE, 0x1c8 */ + u32 clk_src_owr; /* _CLK_SOURCE_OWR, 0x1cc */ + u32 clk_src_nor; /* _CLK_SOURCE_NOR, 0x1d0 */ + u32 clk_src_csite; /* _CLK_SOURCE_CSITE, 0x1d4 */ + u32 clk_src_i2s0; /* _CLK_SOURCE_I2S0, 0x1d8 */ + u32 clk_src_dtv; /* _CLK_SOURCE_DTV, 0x1dc */ + u32 _rsv16[4]; /* 0x1e0-1ec */ + u32 clk_src_msenc; /* _CLK_SOURCE_MSENC, 0x1f0 */ + u32 clk_src_tsec; /* _CLK_SOURCE_TSEC, 0x1f4 */ + u32 _rsv17; /* 0x1f8 */ + u32 clk_src_osc; /* _CLK_SOURCE_OSC, 0x1fc */ + u32 _rsv18[32]; /* 0x200-27c */ + u32 clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + u32 clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + u32 clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + u32 rst_dev_x; /* _RST_DEVICES_X_0, 0x28c */ + u32 rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + u32 rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + u32 clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */ + u32 clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29C */ + u32 clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2A0 */ + u32 rst_dev_y; /* _RST_DEVICES_Y_0, 0x2A4 */ + u32 rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2A8 */ + u32 rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2AC */ + u32 _rsv19[17]; /* 0x2B0-2f0 */ + u32 dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + u32 _rsv20[2]; /* 0x2f8-2fc */ + u32 rst_dev_l_set; /* _RST_DEV_L_SET 0x300 */ + u32 rst_dev_l_clr; /* _RST_DEV_L_CLR 0x304 */ + u32 rst_dev_h_set; /* _RST_DEV_H_SET 0x308 */ + u32 rst_dev_h_clr; /* _RST_DEV_H_CLR 0x30c */ + u32 rst_dev_u_set; /* _RST_DEV_U_SET 0x310 */ + u32 rst_dev_u_clr; /* _RST_DEV_U_CLR 0x314 */ + u32 _rsv21[2]; /* 0x318-31c */ + u32 clk_enb_l_set; /* _CLK_ENB_L_SET 0x320 */ + u32 clk_enb_l_clr; /* _CLK_ENB_L_CLR 0x324 */ + u32 clk_enb_h_set; /* _CLK_ENB_H_SET 0x328 */ + u32 clk_enb_h_clr; /* _CLK_ENB_H_CLR 0x32c */ + u32 clk_enb_u_set; /* _CLK_ENB_U_SET 0x330 */ + u32 clk_enb_u_clr; /* _CLK_ENB_U_CLR 0x334 */ + u32 _rsv22; /* 0x338 */ + u32 ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD, 0x33c */ + u32 rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET, 0x340 */ + u32 rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR, 0x344 */ + u32 clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET, 0x348 */ + u32 clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET, 0x34c */ + u32 _rsv23[2]; /* 0x350-354 */ + u32 rst_dev_v; /* _RST_DEVICES_V, 0x358 */ + u32 rst_dev_w; /* _RST_DEVICES_W, 0x35c */ + u32 clk_out_enb_v; /* _CLK_OUT_ENB_V, 0x360 */ + u32 clk_out_enb_w; /* _CLK_OUT_ENB_W, 0x364 */ + u32 cclkg_brst_pol; /* _CCLKG_BURST_POLICY, 0x368 */ + u32 super_cclkg_div; /* _SUPER_CCLKG_DIVIDER, 0x36c */ + u32 cclklp_brst_pol; /* _CCLKLP_BURST_POLICY, 0x370 */ + u32 super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER, 0x374 */ + u32 clk_cpug_cmplx; /* _CLK_CPUG_CMPLX, 0x378 */ + u32 clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX, 0x37c */ + u32 cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL, 0x380 */ + u32 cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1, 0x384 */ + u32 cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2, 0x388 */ + u32 _rsv24[9]; /* 0x38c-3ac */ + u32 clk_src_g3d2; /* _CLK_SOURCE_G3D2, 0x3b0 */ + u32 clk_src_mselect; /* _CLK_SOURCE_MSELECT, 0x3b4 */ + u32 clk_src_tsensor; /* _CLK_SOURCE_TSENSOR, 0x3b8 */ + u32 clk_src_i2s3; /* _CLK_SOURCE_I2S3, 0x3bc */ + u32 clk_src_i2s4; /* _CLK_SOURCE_I2S4, 0x3c0 */ + u32 clk_src_i2c4; /* _CLK_SOURCE_I2C4, 0x3c4 */ + u32 clk_src_sbc5; /* _CLK_SOURCE_SBC5, 0x3c8 */ + u32 clk_src_sbc6; /* _CLK_SOURCE_SBC6, 0x3cc */ + u32 clk_src_audio; /* _CLK_SOURCE_AUDIO, 0x3d0 */ + u32 _rsv25; /* 0x3d4 */ + u32 clk_src_dam0; /* _CLK_SOURCE_DAM0, 0x3d8 */ + u32 clk_src_dam1; /* _CLK_SOURCE_DAM1, 0x3dc */ + u32 clk_src_dam2; /* _CLK_SOURCE_DAM2, 0x3e0 */ + u32 clk_src_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X,0x3e4 */ + u32 clk_src_actmon; /* _CLK_SOURCE_ACTMON, 0x3e8 */ + u32 clk_src_extperiph1; /* _CLK_SOURCE_EXTPERIPH1, 0x3ec */ + u32 clk_src_extperiph2; /* _CLK_SOURCE_EXTPERIPH2, 0x3f0 */ + u32 clk_src_extperiph3; /* _CLK_SOURCE_EXTPERIPH3, 0x3f4 */ + u32 clk_src_nand_speed; /* _CLK_SOURCE_NAND_SPEED, 0x3f8 */ + u32 clk_src_i2c_slow; /* _CLK_SOURCE_I2C_SLOW, 0x3fc */ + u32 clk_src_sys; /* _CLK_SOURCE_SYS, 0x400 */ + u32 _rsv26[4]; /* 0x404-410 */ + u32 clk_src_sor; /* _CLK_SOURCE_SOR_0, 0x414 */ + u32 _rsv261[2]; /* 0x404-410 */ + u32 clk_src_sata_oob; /* _CLK_SOURCE_SATA_OOB, 0x420 */ + u32 clk_src_sata; /* _CLK_SOURCE_SATA, 0x424 */ + u32 clk_src_hda; /* _CLK_SOURCE_HDA, 0x428 */ + u32 _rsv27; /* 0x42c */ + u32 rst_dev_v_set; /* _RST_DEV_V_SET, 0x430 */ + u32 rst_dev_v_clr; /* _RST_DEV_V_CLR, 0x434 */ + u32 rst_dev_w_set; /* _RST_DEV_W_SET, 0x438 */ + u32 rst_dev_w_clr; /* _RST_DEV_W_CLR, 0x43c */ + u32 clk_enb_v_set; /* _CLK_ENB_V_SET, 0x440 */ + u32 clk_enb_v_clr; /* _CLK_ENB_V_CLR, 0x444 */ + u32 clk_enb_w_set; /* _CLK_ENB_W_SET, 0x448 */ + u32 clk_enb_w_clr; /* _CLK_ENB_W_CLR, 0x44c */ + u32 rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET, 0x450 */ + u32 rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR, 0x454 */ + u32 rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET, 0x458 */ + u32 rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR, 0x45C */ + u32 clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET, 0x460 */ + u32 clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR, 0x464 */ + u32 clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET, 0x468 */ + u32 clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR, 0x46c */ + u32 cpu_cmplx_status; /* _CPU_CMPLX_STATUS, 0x470 */ + u32 _rsv28; /* 0x474 */ + u32 intstatus; /* _INTSTATUS, 0x478 */ + u32 intmask; /* _INTMASK, 0x47c */ + u32 utmip_pll_cfg0; /* _UTMIP_PLL_CFG0, 0x480 */ + u32 utmip_pll_cfg1; /* _UTMIP_PLL_CFG1, 0x484 */ + u32 utmip_pll_cfg2; /* _UTMIP_PLL_CFG2, 0x488 */ + u32 plle_aux; /* _PLLE_AUX, 0x48c */ + u32 sata_pll_cfg0; /* _SATA_PLL_CFG0, 0x490 */ + u32 sata_pll_cfg1; /* _SATA_PLL_CFG1, 0x494 */ + u32 pcie_pll_cfg0; /* _PCIE_PLL_CFG0, 0x498 */ + u32 prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK, 0x49c */ + u32 audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0, 0x4a0 */ + u32 audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1, 0x4a4 */ + u32 audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2, 0x4a8 */ + u32 audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3, 0x4ac */ + u32 audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4, 0x4b0 */ + u32 audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF, 0x4b4 */ + u32 plld2_base; /* _PLLD2_BASE, 0x4b8 */ + u32 plld2_misc; /* _PLLD2_MISC, 0x4bc */ + u32 utmip_pll_cfg3; /* _UTMIP_PLL_CFG3, 0x4c0 */ + u32 pllrefe_base; /* _PLLREFE_BASE, 0x4c4 */ + u32 pllrefe_misc; /* _PLLREFE_MISC, 0x4c8 */ + u32 _rsv29[7]; /* 0x4cc-4e4 */ + u32 pllc2_base; /* _PLLC2_BASE, 0x4e8 */ + u32 pllc2_misc0; /* _PLLC2_MISC_0, 0x4ec */ + u32 pllc2_misc1; /* _PLLC2_MISC_1, 0x4f0 */ + u32 pllc2_misc2; /* _PLLC2_MISC_2, 0x4f4 */ + u32 pllc2_misc3; /* _PLLC2_MISC_3, 0x4f8 */ + u32 pllc3_base; /* _PLLC3_BASE, 0x4fc */ + u32 pllc3_misc0; /* _PLLC3_MISC_0, 0x500 */ + u32 pllc3_misc1; /* _PLLC3_MISC_1, 0x504 */ + u32 pllc3_misc2; /* _PLLC3_MISC_2, 0x508 */ + u32 pllc3_misc3; /* _PLLC3_MISC_3, 0x50c */ + u32 pllx_misc1; /* _PLLX_MISC_1, 0x510 */ + u32 pllx_misc2; /* _PLLX_MISC_2, 0x514 */ + u32 pllx_misc3; /* _PLLX_MISC_3, 0x518 */ + u32 xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0, 0x51c */ + u32 xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG1, 0x520 */ + u32 plle_aux1; /* _PLLE_AUX1, 0x524 */ + u32 pllp_reshift; /* _PLLP_RESHIFT, 0x528 */ + u32 utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0, 0x52c */ + u32 pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0, 0x530 */ + u32 xusb_pll_cfg0; /* _XUSB_PLL_CFG0, 0x534 */ + u32 _rsv30; /* 0x538 */ + u32 clk_cpu_misc; /* _CLK_CPU_MISC, 0x53c */ + u32 clk_cpug_misc; /* _CLK_CPUG_MISC, 0x540 */ + u32 clk_cpulp_misc; /* _CLK_CPULP_MISC, 0x544 */ + u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x548 */ + u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x54c */ + u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x550 */ + u32 _rsv31; /* 0x554 */ + u32 super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER, 0x558 */ + u32 spare_reg0; /* _SPARE_REG0, 0x55c */ + u32 _rsv32[4]; /* 0x560-0x56c */ + u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ + u32 _rsv32_1[7]; /* 0x574-58c */ + u32 plldp_base; /* _PLLDP_BASE, 0x590 */ + u32 plldp_misc; /* _PLLDP_MISC, 0x594 */ + u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ + u32 _rsrv32_2[25]; + u32 clk_src_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */ + u32 clk_src_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON 0x604 */ + u32 clk_src_xusb_fs; /* _CLK_SOURCE_XUSB_FS 0x608 */ + u32 clk_src_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV 0x60c */ + u32 clk_src_xusb_ss; /* _CLK_SOURCE_XUSB_SS 0x610 */ + u32 clk_src_cilab; /* _CLK_SOURCE_CILAB 0x614 */ + u32 clk_src_cilcd; /* _CLK_SOURCE_CILCD 0x618 */ + u32 clk_src_cile; /* _CLK_SOURCE_CILE 0x61c */ + u32 clk_src_dsia_lp; /* _CLK_SOURCE_DSIA_LP 0x620 */ + u32 clk_src_dsib_lp; /* _CLK_SOURCE_DSIB_LP 0x624 */ + u32 clk_src_entropy; /* _CLK_SOURCE_ENTROPY 0x628 */ + u32 clk_src_dvfs_ref; /* _CLK_SOURCE_DVFS_REF 0x62c */ + u32 clk_src_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC 0x630 */ + u32 clk_src_traceclkin; /* _CLK_SOURCE_TRACECLKIN 0x634 */ + u32 clk_src_adx0; /* _CLK_SOURCE_ADX0 0x638 */ + u32 clk_src_amx0; /* _CLK_SOURCE_AMX0 0x63c */ + u32 clk_src_emc_latency; /* _CLK_SOURCE_EMC_LATENCY 0x640 */ + u32 clk_src_soc_therm; /* _CLK_SOURCE_SOC_THERM 0x644 */ + u32 _rsv33[5]; /* 0x648-658 */ + u32 clk_src_i2c6; /* _CLK_SOURCE_I2C6, 0x65c */ + u32 clk_src_mipibif; /* _CLK_SOURCE_MIPIBIF, 0x660 */ + u32 clk_src_emc_dll; /* _CLK_SOURCE_EMC_DLL, 0x664 */ + u32 _rsv34; /* 0x668 */ + u32 clk_src_uart_fst_mipi_cal; /* _CLK_SOURCE_UART_FST_MIP_CAL, 0x66c */ + u32 _rsv35[21]; /* 0x670-6c0 */ + u32 clk_src_qspi; /* _CLK_SOURCE_QSPI 0x6C4 */ +}; +check_member(clk_rst_ctlr, clk_src_qspi, 0x6C4); + +#define CLK_RST_REG(field_) \ + (&(((struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE)->field_)) + +/* L, H, U, V, W, X, Y */ +#define DEV_CONFIG_BLOCKS 7 + +#define TEGRA_DEV_L 0 +#define TEGRA_DEV_H 1 +#define TEGRA_DEV_U 2 +#define TEGRA_DEV_V 0 +#define TEGRA_DEV_W 1 + +#define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE) + +/* Bits to enable/reset modules */ +#define CLK_ENB_CPU (1 << 0) +#define SWR_TRIG_SYS_RST (1 << 2) +#define SWR_CSITE_RST (1 << 9) +#define CLK_ENB_CSITE (1 << 9) +#define CLK_ENB_EMC_DLL (1 << 14) + +/* _CCLK_BURST_POLICY 0x20 */ +#define CCLK_BURST_POLICY_VAL 0x20008888 +/* CLK_M divisor */ +#define CLK_M_DIVISOR_MASK (0x3 << 2) +#define CLK_M_DIVISOR_BY_2 (1 << 2) + +/* CRC_SUPER_CCLK_DIVIDER_0 0x24 */ +#define SUPER_CDIV_ENB_ENABLE (1 << 31) + +/* CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48 */ +#define EN_PPSB_STOPCLK (1 << 0) + +/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 (0x4C) */ +#define CPU3_CLK_STP_SHIFT 11 +#define CPU2_CLK_STP_SHIFT 10 +#define CPU1_CLK_STP_SHIFT 9 +#define CPU0_CLK_STP_SHIFT 8 +#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) + +/* CRC_OSC_CTRL_0 0x50 */ +#define OSC_FREQ_SHIFT 28 +#define OSC_FREQ_MASK (0xf << OSC_FREQ_SHIFT) +#define OSC_PREDIV_SHIFT 26 +#define OSC_PREDIV_MASK (0x3 << OSC_PREDIV_SHIFT) +#define OSC_XOFS_SHIFT 4 +#define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) +#define OSC_DRIVE_STRENGTH 7 +#define OSC_XOBP (1 << 1) +#define OSC_XOE (1 << 0) + +enum { + OSC_FREQ_12 = 8, /* 12.0MHz */ + OSC_FREQ_13 = 0, /* 13.0MHz */ + OSC_FREQ_16P8 = 1, /* 16.8MHz */ + OSC_FREQ_19P2 = 4, /* 19.2MHz */ + OSC_FREQ_26 = 12, /* 26.0MHz */ + OSC_FREQ_38P4 = 5, /* 38.4MHz */ + OSC_FREQ_48 = 9, /* 48.0MHz */ +}; + +/* CLK_RST_CONTROLLER_PLL*_BASE_0 */ +#define PLL_BASE_BYPASS (1U << 31) +#define PLL_BASE_ENABLE (1U << 30) +#define PLL_BASE_REF_DIS (1U << 29) +#define PLL_BASE_OVRRIDE (1U << 28) +#define PLL_BASE_LOCK (1U << 27) +#define PLLC_BASE_LOCK (1U << 26) + +#define PLL_BASE_DIVP_SHIFT 20 +#define PLL_BASE_DIVP_MASK (7U << PLL_BASE_DIVP_SHIFT) + +#define PLL_BASE_DIVN_SHIFT 8 +#define PLL_BASE_DIVN_MASK (0x3ffU << PLL_BASE_DIVN_SHIFT) + +#define PLL_BASE_DIVM_SHIFT 0 +#define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT) + +/* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */ +#define PLLCX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT) +#define PLLM_BASE_DIVP_MASK (0x1fU << PLL_BASE_DIVP_SHIFT) +#define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT) +#define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT) + +/* Added based on T210 TRM */ +#define PLLC_MISC_RESET (1U << 30) +#define PLLC_MISC_1_IDDQ (1U << 27) +#define PLLD_N_SHIFT 11 +#define PLLD_M_SHIFT 0 +#define PLLD_P_SHIFT 20 +#define PLLD_MISC1_SETUP 0x20 +#define PLLD_MISC_EN_SDM (1 << 16) +#define PLLD_MISC_SDM_DIN 0x9aa + +/* PLLM specific registers */ +#define PLLM_MISC1_SETUP_SHIFT 0 +#define PLLM_MISC1_PD_LSHIFT_PH45_SHIFT 28 +#define PLLM_MISC1_PD_LSHIFT_PH90_SHIFT 29 +#define PLLM_MISC1_PD_LSHIFT_PH135_SHIFT 30 +#define PLLM_MISC2_KCP_SHIFT 1 +#define PLLM_MISC2_KVCO_SHIFT 0 +#define PLLM_OUT1_RSTN_RESET_DISABLE (1 << 0) +#define PLLM_EN_LCKDET (1 << 4) + +/* PLLU specific registers */ +#define PLLU_MISC_IDDQ (1U << 31) + +/* UTMIP PLL specific registers */ +#define UTMIP_CFG0_PLL_MDIV_SHIFT (8) +#define UTMIP_CFG0_PLL_NDIV_SHIFT (16) +#define UTMIP_CFG1_XTAL_FREQ_COUNT_SHIFT (0) +#define UTMIP_CFG1_FORCE_PLL_ACTIVE_POWERDOWN_DISABLE (0 << 12) +#define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERDOWN_DISABLE (0 << 14) +#define UTMIP_CFG1_FORCE_PLL_ENABLE_POWERUP_ENABLE (1 << 15) +#define UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE (1 << 16) +#define UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT (27) +#define UTMIP_CFG2_FORCE_PD_SAMP_A_POWERDOWN_DISABLE (0 << 0) +#define UTMIP_CFG2_FORCE_PD_SAMP_B_POWERDOWN_DISABLE (0 << 2) +#define UTMIP_CFG2_FORCE_PD_SAMP_C_POWERDOWN_DISABLE (0 << 4) +#define UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT (6) +#define UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT (18) +#define UTMIP_CFG2_PHY_XTAL_CLOCKEN (1U << 30) + +/* Generic, indiscriminate divisor mask. May catch some innocent bystander bits + * on the side that we don't particularly care about. */ +#define PLL_BASE_DIV_MASK (0xffffff) + +/* CLK_RST_CONTROLLER_PLL*_OUT*_0 */ +#define PLL_OUT_RSTN (1 << 0) +#define PLL_OUT_CLKEN (1 << 1) +#define PLL_OUT_OVR (1 << 2) + +#define PLL_OUT_RATIO_SHIFT 8 +#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) + +#define PLL_OUT1_SHIFT 0 +#define PLL_OUT2_SHIFT 16 +#define PLL_OUT3_SHIFT 0 +#define PLL_OUT4_SHIFT 16 + +/* This bit is different all over the place. */ +#define PLLDPD2_MISC_LOCK_ENABLE (1 << 30) +#define PLLU_MISC_LOCK_ENABLE (1 << 29) +#define PLLD_MISC_LOCK_ENABLE (1 << 18) +#define PLLD_MISC_CLK_ENABLE (1 << 21) +#define PLLPAXS_MISC_LOCK_ENABLE (1 << 18) +#define PLLE_MISC_LOCK_ENABLE (1 << 9) + +/* PLLX_BASE_0 0xe0 */ +#define PLLX_BASE_PLLX_ENABLE (1 << 30) + +/* CLK_RST_CONTROLLER_PLLX_MISC_3 */ +#define PLLX_IDDQ_SHIFT 3 +#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) + +#define CLK_DIVISOR_MASK (0xffff) + +#define CLK_SOURCE_SHIFT 29 +#define CLK_SOURCE_MASK (0x7 << CLK_SOURCE_SHIFT) + +#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ (1 << 16) +#define EMC_2X_CLK_SRC_SHIFT 29 +#define PLLM_UD 4 + +#define CLK_UART_DIV_OVERRIDE (1 << 24) + +/* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ +#define SCLK_SYS_STATE_SHIFT 28U +#define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT) +enum { + SCLK_SYS_STATE_STDBY, + SCLK_SYS_STATE_IDLE, + SCLK_SYS_STATE_RUN, + SCLK_SYS_STATE_IRQ = 4U, + SCLK_SYS_STATE_FIQ = 8U, +}; +#define SCLK_COP_FIQ_MASK (1 << 27) +#define SCLK_CPU_FIQ_MASK (1 << 26) +#define SCLK_COP_IRQ_MASK (1 << 25) +#define SCLK_CPU_IRQ_MASK (1 << 24) + +#define SCLK_FIQ_SHIFT 12 +#define SCLK_FIQ_MASK (7 << SCLK_FIQ_SHIFT) +#define SCLK_IRQ_SHIFT 8 +#define SCLK_IRQ_MASK (7 << SCLK_FIQ_SHIFT) +#define SCLK_RUN_SHIFT 4 +#define SCLK_RUN_MASK (7 << SCLK_FIQ_SHIFT) +#define SCLK_IDLE_SHIFT 0 +#define SCLK_IDLE_MASK (7 << SCLK_FIQ_SHIFT) +enum { + SCLK_SOURCE_CLKM, + SCLK_SOURCE_PLLC_OUT1, + SCLK_SOURCE_PLLP_OUT4, + SCLK_SOURCE_PLLP_OUT3, + SCLK_SOURCE_PLLP_OUT2, + SCLK_SOURCE_PLLC_OUT0, + SCLK_SOURCE_CLKS, + SCLK_SOURCE_PLLM_OUT1, +}; + +/* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2c */ +#define SCLK_DIV_ENB (1 << 31) +#define SCLK_DIVIDEND_SHIFT 8 +#define SCLK_DIVIDEND_MASK (0xff << SCLK_DIVIDEND_SHIFT) +#define SCLK_DIVISOR_SHIFT 0 +#define SCLK_DIVISOR_MASK (0xff << SCLK_DIVISOR_SHIFT) + +/* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */ +#define HCLK_DISABLE (1 << 7) +#define HCLK_DIVISOR_SHIFT 4 +#define HCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) +#define PCLK_DISABLE (1 << 3) +#define PCLK_DIVISOR_SHIFT 0 +#define PCLK_DIVISOR_MASK (3 << AHB_RATE_SHIFT) + +/* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ +#define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) + +/* CRC_CLK_ENB_V_SET_0 0x440 */ +#define SET_CLK_ENB_CPUG_ENABLE (1 << 0) +#define SET_CLK_ENB_CPULP_ENABLE (1 << 1) +#define SET_CLK_ENB_MSELECT_ENABLE (1 << 3) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */ +#define PLLU_POWERDOWN (1 << 16) +#define PLL_ENABLE_POWERDOWN (1 << 14) +#define PLL_ACTIVE_POWERDOWN (1 << 12) + +/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */ +#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) +#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) + +// CCLK_BRST_POL +enum { + CRC_CCLK_BRST_POL_PLLX_OUT0 = 0x8, + CRC_CCLK_BRST_POL_CPU_STATE_RUN = 0x2 +}; + +// SUPER_CCLK_DIVIDER +enum { + CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 +}; + +// CLK_CPU_CMPLX_CLR +enum { + CRC_CLK_CLR_CPU0_STP = 0x1 << 8, + CRC_CLK_CLR_CPU1_STP = 0x1 << 9, + CRC_CLK_CLR_CPU2_STP = 0x1 << 10, + CRC_CLK_CLR_CPU3_STP = 0x1 << 11 +}; + +// RST_CPUG_CMPLX_CLR +enum { + CRC_RST_CPUG_CLR_CPU0 = 0x1 << 0, + CRC_RST_CPUG_CLR_CPU1 = 0x1 << 1, + CRC_RST_CPUG_CLR_CPU2 = 0x1 << 2, + CRC_RST_CPUG_CLR_CPU3 = 0x1 << 3, + CRC_RST_CPUG_CLR_DBG0 = 0x1 << 12, + CRC_RST_CPUG_CLR_DBG1 = 0x1 << 13, + CRC_RST_CPUG_CLR_DBG2 = 0x1 << 14, + CRC_RST_CPUG_CLR_DBG3 = 0x1 << 15, + CRC_RST_CPUG_CLR_CORE0 = 0x1 << 16, + CRC_RST_CPUG_CLR_CORE1 = 0x1 << 17, + CRC_RST_CPUG_CLR_CORE2 = 0x1 << 18, + CRC_RST_CPUG_CLR_CORE3 = 0x1 << 19, + CRC_RST_CPUG_CLR_CX0 = 0x1 << 20, + CRC_RST_CPUG_CLR_CX1 = 0x1 << 21, + CRC_RST_CPUG_CLR_CX2 = 0x1 << 22, + CRC_RST_CPUG_CLR_CX3 = 0x1 << 23, + CRC_RST_CPUG_CLR_L2 = 0x1 << 24, + CRC_RST_CPUG_CLR_NONCPU = 0x1 << 29, + CRC_RST_CPUG_CLR_PDBG = 0x1 << 30, +}; + +// RST_CPULP_CMPLX_CLR +enum { + CRC_RST_CPULP_CLR_CPU0 = 0x1 << 0, + CRC_RST_CPULP_CLR_DBG0 = 0x1 << 12, + CRC_RST_CPULP_CLR_CORE0 = 0x1 << 16, + CRC_RST_CPULP_CLR_CX0 = 0x1 << 20, + CRC_RST_CPULP_CLR_L2 = 0x1 << 24, + CRC_RST_CPULP_CLR_NONCPU = 0x1 << 29, + CRC_RST_CPULP_CLR_PDBG = 0x1 << 30, +}; + +#define TIMERUS_CNTR_1US 0x0 +#define TIMERUS_USEC_CFG 0x4 +#define TIMERUS_USEC_CFG_19P2_CLK_M 0x045F + +#endif /* _TEGRA210_CLK_RST_H_ */ diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h new file mode 100644 index 0000000000..ff9b282eaa --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -0,0 +1,442 @@ +/* + * Copyright 2014 Google Inc. + * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_CLOCK_H__ +#define __SOC_NVIDIA_TEGRA210_CLOCK_H__ + +#include <arch/hlt.h> +#include <arch/io.h> +#include <console/console.h> +#include <soc/clk_rst.h> +#include <stdint.h> +#include <stdlib.h> + +enum { + CLK_L_CPU = 0x1 << 0, + CLK_L_COP = 0x1 << 1, + CLK_L_TRIG_SYS = 0x1 << 2, + CLK_L_RTC = 0x1 << 4, + CLK_L_TMR = 0x1 << 5, + CLK_L_UARTA = 0x1 << 6, + CLK_L_UARTB = 0x1 << 7, + CLK_L_GPIO = 0x1 << 8, + CLK_L_SDMMC2 = 0x1 << 9, + CLK_L_SPDIF = 0x1 << 10, + CLK_L_I2S2 = 0x1 << 11, + CLK_L_I2C1 = 0x1 << 12, + CLK_L_NDFLASH = 0x1 << 13, + CLK_L_SDMMC1 = 0x1 << 14, + CLK_L_SDMMC4 = 0x1 << 15, + CLK_L_PWM = 0x1 << 17, + CLK_L_I2S3 = 0x1 << 18, + CLK_L_EPP = 0x1 << 19, + CLK_L_VI = 0x1 << 20, + CLK_L_2D = 0x1 << 21, + CLK_L_USBD = 0x1 << 22, + CLK_L_ISP = 0x1 << 23, + CLK_L_3D = 0x1 << 24, + CLK_L_DISP2 = 0x1 << 26, + CLK_L_DISP1 = 0x1 << 27, + CLK_L_HOST1X = 0x1 << 28, + CLK_L_VCP = 0x1 << 29, + CLK_L_I2S1 = 0x1 << 30, + CLK_L_CACHE2 = 0x1 << 31, + + CLK_H_MEM = 0x1 << 0, + CLK_H_AHBDMA = 0x1 << 1, + CLK_H_APBDMA = 0x1 << 2, + CLK_H_KBC = 0x1 << 4, + CLK_H_STAT_MON = 0x1 << 5, + CLK_H_PMC = 0x1 << 6, + CLK_H_FUSE = 0x1 << 7, + CLK_H_KFUSE = 0x1 << 8, + CLK_H_SBC1 = 0x1 << 9, + CLK_H_SNOR = 0x1 << 10, + CLK_H_JTAG2TBC = 0x1 << 11, + CLK_H_SBC2 = 0x1 << 12, + CLK_H_SBC3 = 0x1 << 14, + CLK_H_I2C5 = 0x1 << 15, + CLK_H_DSI = 0x1 << 16, + CLK_H_HSI = 0x1 << 18, + CLK_H_HDMI = 0x1 << 19, + CLK_H_CSI = 0x1 << 20, + CLK_H_I2C2 = 0x1 << 22, + CLK_H_UARTC = 0x1 << 23, + CLK_H_MIPI_CAL = 0x1 << 24, + CLK_H_EMC = 0x1 << 25, + CLK_H_USB2 = 0x1 << 26, + CLK_H_USB3 = 0x1 << 27, + CLK_H_MPE = 0x1 << 28, + CLK_H_VDE = 0x1 << 29, + CLK_H_BSEA = 0x1 << 30, + CLK_H_BSEV = 0x1 << 31, + + CLK_U_UARTD = 0x1 << 1, + CLK_U_UARTE = 0x1 << 2, + CLK_U_I2C3 = 0x1 << 3, + CLK_U_SBC4 = 0x1 << 4, + CLK_U_SDMMC3 = 0x1 << 5, + CLK_U_PCIE = 0x1 << 6, + CLK_U_OWR = 0x1 << 7, + CLK_U_AFI = 0x1 << 8, + CLK_U_CSITE = 0x1 << 9, + CLK_U_PCIEXCLK = 0x1 << 10, + CLK_U_AVPUCQ = 0x1 << 11, + CLK_U_TRACECLKIN = 0x1 << 13, + CLK_U_SOC_THERM = 0x1 << 14, + CLK_U_DTV = 0x1 << 15, + CLK_U_NAND_SPEED = 0x1 << 16, + CLK_U_I2C_SLOW = 0x1 << 17, + CLK_U_DSIB = 0x1 << 18, + CLK_U_TSEC = 0x1 << 19, + CLK_U_IRAMA = 0x1 << 20, + CLK_U_IRAMB = 0x1 << 21, + CLK_U_IRAMC = 0x1 << 22, + + // Clock reset. + CLK_U_EMUCIF = 0x1 << 23, + // Clock enable. + CLK_U_IRAMD = 0x1 << 23, + + CLK_U_CRAM2 = 0x2 << 24, + CLK_U_XUSB_HOST = 0x1 << 25, + CLK_U_MSENC = 0x1 << 27, + CLK_U_SUS_OUT = 0x1 << 28, + CLK_U_DEV2_OUT = 0x1 << 29, + CLK_U_DEV1_OUT = 0x1 << 30, + CLK_U_XUSB_DEV = 0x1 << 31, + + CLK_V_CPUG = 0x1 << 0, + CLK_V_CPULP = 0x1 << 1, + CLK_V_3D2 = 0x1 << 2, + CLK_V_MSELECT = 0x1 << 3, + CLK_V_I2S4 = 0x1 << 5, + CLK_V_I2S5 = 0x1 << 6, + CLK_V_I2C4 = 0x1 << 7, + CLK_V_SBC5 = 0x1 << 8, + CLK_V_SBC6 = 0x1 << 9, + CLK_V_AHUB = 0x1 << 10, + CLK_V_APB2APE = 0x1 << 11, + CLK_V_HDA2CODEC_2X = 0x1 << 15, + CLK_V_ATOMICS = 0x1 << 16, + CLK_V_ACTMON = 0x1 << 23, + CLK_V_EXTPERIPH1 = 0x1 << 24, + CLK_V_SATA = 0x1 << 28, + CLK_V_HDA = 0x1 << 29, + + CLK_W_HDA2HDMICODEC = 0x1 << 0, + CLK_W_SATACOLD = 0x1 << 1, + CLK_W_CEC = 0x1 << 8, + CLK_W_XUSB_PADCTL = 0x1 << 14, + CLK_W_ENTROPY = 0x1 << 21, + CLK_W_DVFS = 0x1 << 27, + CLK_W_XUSB_SS = 0x1 << 28, + + CLK_X_GPU = 0x1 << 24, + CLK_X_SOR1 = 0x1 << 23, + CLK_X_SOR0 = 0x1 << 22, + CLK_X_DPAUX = 0x1 << 21, + CLK_X_VIC = 0x1 << 18, + CLK_X_UART_FST_MIPI_CAL = 0x1 << 17, + CLK_X_MIPIBIF = 0x1 << 13, + CLK_X_I2C6 = 0x1 << 6, + CLK_X_ETR = 0x1 << 3, + CLK_X_SPARE = 0x1 << 0, + + CLK_Y_APE = 0x1 << 6, + CLK_Y_QSPI = 0x1 << 19, +}; + +enum { + PLLP = 0, + PLLC2 = 1, + PLLC = 2, + PLLC_OUT1 = 3, + PLLM = 4, + CLK_M = 5, + CLK_S = 6, + PLLE = 7, + PLLA = 8, + PLLD = 9, + PLLD2 = 10, + PLLC4_OUT0 = 11, + PLLC4_OUT1 = 12, + PLLC4_OUT2 = 13, + PLLC4_OUT3 = 14, + PLLC4_OUT0_L = 15, + PLLC4_OUT1_L = 16, + PLLC4_OUT2_L = 17, + PLLD_OUT0 = 18, + PLLP_OUT3 = 19, + PLLC2_OUT0 = 20, + UNUSED0 = 100, + UNUSED1 = 101, + UNUSED2 = 102, + UNUSED3 = 103, + UNUSED4 = 104, + UNUSED5 = 105, + UNUSED6 = 106, + UNUSED7 = 107, +}; + +#define CLK_SRC_DEV_ID(dev, src) CLK_SRC_##dev##_##src +#define CLK_SRC_FREQ_ID(dev, src) CLK_SRC_FREQ_##dev##_##src + +#define CLK_SRC_DEVICE(dev, a, b, c, d, e, f, g, h) \ + CLK_SRC_DEV_ID(dev, a) = 0, \ + CLK_SRC_DEV_ID(dev, b) = 1, \ + CLK_SRC_DEV_ID(dev, c) = 2, \ + CLK_SRC_DEV_ID(dev, d) = 3, \ + CLK_SRC_DEV_ID(dev, e) = 4, \ + CLK_SRC_DEV_ID(dev, f) = 5, \ + CLK_SRC_DEV_ID(dev, g) = 6, \ + CLK_SRC_DEV_ID(dev, h) = 7, \ + CLK_SRC_FREQ_ID(dev, a) = a, \ + CLK_SRC_FREQ_ID(dev, b) = b, \ + CLK_SRC_FREQ_ID(dev, c) = c, \ + CLK_SRC_FREQ_ID(dev, d) = d, \ + CLK_SRC_FREQ_ID(dev, e) = e, \ + CLK_SRC_FREQ_ID(dev, f) = f, \ + CLK_SRC_FREQ_ID(dev, g) = g, \ + CLK_SRC_FREQ_ID(dev, h) = h + +enum { + CLK_SRC_DEVICE(disp1, PLLP, PLLD, PLLD_OUT0, UNUSED3, UNUSED4, PLLD2, + CLK_M, UNUSED7), + CLK_SRC_DEVICE(host1x, PLLC4_OUT1, PLLC2, PLLC, PLLC4_OUT2, PLLP, CLK_M, + PLLA, PLLC4_OUT0), + CLK_SRC_DEVICE(I2C1, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1, + CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(I2C2, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1, + CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(I2C3, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1, + CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(I2C5, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1, + CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(I2C6, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1, + CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(I2S1, PLLA, UNUSED1, CLK_S, UNUSED3, PLLP, UNUSED5, + CLK_M, UNUSED7), + CLK_SRC_DEVICE(mselect, PLLP, PLLC2, PLLC, PLLC4_OUT2, PLLC4_OUT1, + CLK_S, CLK_M, PLLC4_OUT0), + CLK_SRC_DEVICE(SPI1, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1, + CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(SPI4, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, PLLC4_OUT1, + CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(SDMMC1, PLLP, PLLA, PLLC, PLLC4_OUT2, PLLM, PLLE, CLK_M, + PLLC4_OUT0), + CLK_SRC_DEVICE(SDMMC4, PLLP, PLLC4_OUT2_L, PLLC4_OUT0_L, PLLC4_OUT2, + PLLC4_OUT1, PLLC4_OUT1_L, CLK_M, PLLC4_OUT0), + CLK_SRC_DEVICE(UARTA, PLLP, PLLC2, PLLC, PLLC4_OUT0, UNUSED4, + PLLC4_OUT1, CLK_M, PLLC4_OUT2), + CLK_SRC_DEVICE(i2s1, PLLA, UNUSED1, CLK_S, UNUSED3, PLLP, UNUSED5, + CLK_M, UNUSED7), + CLK_SRC_DEVICE(extperiph1, PLLA, CLK_S, PLLP, CLK_M, PLLE, UNUSED5, + UNUSED6, UNUSED7), + CLK_SRC_DEVICE(QSPI, PLLP, PLLC_OUT1, PLLC, UNUSED3, PLLC4_OUT2, + PLLC4_OUT1, CLK_M, PLLC4_OUT0), + CLK_SRC_DEVICE(uart_fst_mipi_cal, PLLP_OUT3, PLLP, PLLC, UNUSED3, PLLC2_OUT0, + UNUSED5, CLK_M, UNUSED7), +}; + +/* PLL stabilization delay in usec */ +#define CLOCK_PLL_STABLE_DELAY_US 300 + +#define IO_STABILIZATION_DELAY (2) +#define LOGIC_STABILIZATION_DELAY (2) + +/* Calculate clock fractional divider value from ref and target frequencies. + * This is for a U7.1 format. This is not well written up in the book and + * there have been some questions about this macro, so here we go. + * U7.1 format is defined as (ddddddd+1) + (h*.5) + * The lowest order bit is actually a fractional bit. + * Hence, the divider can be thought of as 9 bits. + * So: + * divider = ((ref/freq) << 1 - 1) (upper 7 bits) | + * (ref/freq & 1) (low order half-bit) + * however we can't do fractional arithmetic ... these are integers! + * So we normalize by shifting the result left 1 bit, and extracting + * ddddddd and h directly to the returned u8. + * divider = 2*(ref/freq); + * We want to + * preserve 7 bits of divisor and one bit of fraction, in 8 bits, as well as + * subtract one from ddddddd. Since we computed ref*2, the dddddd is now nicely + * situated in the upper 7 bits, and the h is sitting there in the low order + * bit. To subtract 1 from ddddddd, just subtract 2 from the 8-bit number + * and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you + * will assign this to a u8, it gets nicely truncated for you. + */ +#define CLK_DIVIDER(REF, FREQ) (div_round_up(((REF) * 2), (FREQ)) - 2) + +/* Calculate clock frequency value from reference and clock divider value + * The discussion in the book is pretty lacking. + * The idea is that we need to divide a ref clock by a divisor + * in U7.1 format, where 7 upper bits are the integer + * and lowest order bit is a fraction. + * from the book, U7.1 is (ddddddd+1) + (h*.5) + * To normalize to an actual number, we might do this: + * ((d>>7+1)&0x7f) + (d&1 >> 1) + * but as you might guess, the low order bit would be lost. + * Since we can't express the fractional bit, we need to multiply it all by 2. + * ((d + 2)&0xfe) + (d & 1) + * Since we're just adding +2, the lowest order bit is preserved. Hence + * (d+2) is the same as ((d + 2)&0xfe) + (d & 1) + * + * Since you multiply denominator * 2 (by NOT shifting it), + * you multiply numerator * 2 to cancel it out. + */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2)) + +static inline void _clock_set_div(u32 *reg, const char *name, u32 div, + u32 div_mask, u32 src) +{ + // The I2C and UART divisors are 16 bit while all the others are 8 bit. + // The I2C clocks are handled by the specialized macro below, but the + // UART clocks aren't. Don't use this function on UART clocks. + if (div & ~div_mask) { + printk(BIOS_ERR, "%s clock divisor overflow!", name); + hlt(); + } + clrsetbits_le32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK, + src << CLK_SOURCE_SHIFT | div); +} + +#define get_i2c_clk_div(src,freq) (div_round_up(src, (freq) * (0x19 + 1) * 8) - 1) +#define get_clk_div(src,freq) CLK_DIVIDER(src,freq) +#define CLK_DIV_MASK 0xff +#define CLK_DIV_MASK_I2C 0xffff + +#define clock_configure_source(device, src, freq) \ + _clock_set_div(CLK_RST_REG(clk_src_##device), #device, \ + get_clk_div(TEGRA_##src##_KHZ, freq), CLK_DIV_MASK, \ + CLK_SRC_DEV_ID(device, src)) + +/* soc-specific */ +#define TEGRA_CLK_M_KHZ (clock_get_osc_khz()/2) +#define TEGRA_PLLX_KHZ CONFIG_PLLX_KHZ +#define TEGRA_PLLP_KHZ (408000) +#define TEGRA_PLLP_OUT3_KHZ (68000) +#define TEGRA_PLLC_KHZ (600000) +#define TEGRA_PLLD_KHZ (925000) +#define TEGRA_PLLD_OUT0_KHZ (TEGRA_PLLD_KHZ/2) +#define TEGRA_PLLU_KHZ (960000) + +#define clock_enable(l, h, u, v, w, x, y) \ + do { \ + u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \ + clock_enable_regs(bits); \ + } while (0) + +#define clock_disable(l, h, u, v, w, x, y) \ + do { \ + u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \ + clock_disable_regs(bits); \ + } while (0) + +#define clock_set_reset(l, h, u, v, w, x, y) \ + do { \ + u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \ + clock_set_reset_regs(bits); \ + } while (0) + +#define clock_clr_reset(l, h, u, v, w, x, y) \ + do { \ + u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y}; \ + clock_clr_reset_regs(bits); \ + } while (0) + +#define clock_enable_l(l) clock_enable(l, 0, 0, 0, 0, 0, 0) +#define clock_enable_h(h) clock_enable(0, h, 0, 0, 0, 0, 0) +#define clock_enable_u(u) clock_enable(0, 0, u, 0, 0, 0, 0) +#define clock_enable_v(v) clock_enable(0, 0, 0, v, 0, 0, 0) +#define clock_enable_w(w) clock_enable(0, 0, 0, 0, w, 0, 0) +#define clock_enable_x(x) clock_enable(0, 0, 0, 0, 0, x, 0) +#define clock_enable_y(y) clock_enable(0, 0, 0, 0, 0, 0, y) + +#define clock_disable_l(l) clock_disable(l, 0, 0, 0, 0, 0, 0) +#define clock_disable_h(h) clock_disable(0, h, 0, 0, 0, 0, 0) +#define clock_disable_u(u) clock_disable(0, 0, u, 0, 0, 0, 0) +#define clock_disable_v(v) clock_disable(0, 0, 0, v, 0, 0, 0) +#define clock_disable_w(w) clock_disable(0, 0, 0, 0, w, 0, 0) +#define clock_disable_x(x) clock_disable(0, 0, 0, 0, 0, x, 0) +#define clock_disable_y(y) clock_disable(0, 0, 0, 0, 0, 0, y) + +#define clock_set_reset_l(l) clock_set_reset(l, 0, 0, 0, 0, 0, 0) +#define clock_set_reset_h(h) clock_set_reset(0, h, 0, 0, 0, 0, 0) +#define clock_set_reset_u(u) clock_set_reset(0, 0, u, 0, 0, 0, 0) +#define clock_set_reset_v(v) clock_set_reset(0, 0, 0, v, 0, 0, 0) +#define clock_set_reset_w(w) clock_set_reset(0, 0, 0, 0, w, 0, 0) +#define clock_set_reset_x(x) clock_set_reset(0, 0, 0, 0, 0, x, 0) +#define clock_set_reset_y(x) clock_set_reset(0, 0, 0, 0, 0, y, 0) + +#define clock_clr_reset_l(l) clock_clr_reset(l, 0, 0, 0, 0, 0, 0) +#define clock_clr_reset_h(h) clock_clr_reset(0, h, 0, 0, 0, 0, 0) +#define clock_clr_reset_u(u) clock_clr_reset(0, 0, u, 0, 0, 0, 0) +#define clock_clr_reset_v(v) clock_clr_reset(0, 0, 0, v, 0, 0, 0) +#define clock_clr_reset_w(w) clock_clr_reset(0, 0, 0, 0, w, 0, 0) +#define clock_clr_reset_x(x) clock_clr_reset(0, 0, 0, 0, 0, x, 0) +#define clock_clr_reset_y(y) clock_clr_reset(0, 0, 0, 0, 0, 0, y) + +#define clock_enable_clear_reset_l(l) \ + clock_enable_clear_reset(l, 0, 0, 0, 0, 0, 0) +#define clock_enable_clear_reset_h(h) \ + clock_enable_clear_reset(0, h, 0, 0, 0, 0, 0) +#define clock_enable_clear_reset_u(u) \ + clock_enable_clear_reset(0, 0, u, 0, 0, 0, 0) +#define clock_enable_clear_reset_v(v) \ + clock_enable_clear_reset(0, 0, 0, v, 0, 0, 0) +#define clock_enable_clear_reset_w(w) \ + clock_enable_clear_reset(0, 0, 0, 0, w, 0, 0) +#define clock_enable_clear_reset_x(x) \ + clock_enable_clear_reset(0, 0, 0, 0, 0, x, 0) +#define clock_enable_clear_reset_y(y) \ + clock_enable_clear_reset(0, 0, 0, 0, 0, 0, y) + +int clock_get_osc_khz(void); +int clock_get_pll_input_khz(void); +/* + * Configure PLLD to requested frequency. Returned value is closest match + * within the PLLD's constraints or 0 if an error. + */ +u32 clock_configure_plld(u32 frequency); +void clock_early_uart(void); +void clock_external_output(int clk_id); +void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 kvco, u32 kcp, + u32 stable_time, u32 emc_source, u32 same_freq); +void clock_cpu0_config(void); +void clock_halt_avp(void); +void clock_enable_regs(u32 bits[DEV_CONFIG_BLOCKS]); +void clock_disable_regs(u32 bits[DEV_CONFIG_BLOCKS]); +void clock_set_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]); +void clock_clr_reset_regs(u32 bits[DEV_CONFIG_BLOCKS]); +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x, u32 y); +void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg); +void clock_reset_l(u32 l); +void clock_reset_h(u32 h); +void clock_reset_u(u32 u); +void clock_reset_v(u32 v); +void clock_reset_w(u32 w); +void clock_reset_x(u32 x); +void clock_reset_y(u32 y); +void clock_init(void); +void clock_init_arm_generic_timer(void); +void sor_clock_stop(void); +void sor_clock_start(void); +void clock_enable_audio(void); + +#endif /* __SOC_NVIDIA_TEGRA210_CLOCK_H__ */ + diff --git a/src/soc/nvidia/tegra210/include/soc/clst_clk.h b/src/soc/nvidia/tegra210/include/soc/clst_clk.h new file mode 100644 index 0000000000..e0de867def --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/clst_clk.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA210_CLST_CLK_H_ +#define _TEGRA210_CLST_CLK_H_ + +/* Cluster Clock (CLUSTER_CLOCKS_PUBLIC_) regs */ +struct __attribute__ ((__packed__)) clst_clk_ctlr { + u32 pllx_base; /* _PLLX_BASE, 0x000 */ + u32 pllx_misc; /* _PLLX_MISC, 0x004 */ + u32 pllx_misc1; /* _PLLX_MISC_1, 0x008 */ + u32 pllx_misc2; /* _PLLX_MISC_2, 0x00c */ + u32 pllx_misc3; /* _PLLX_MISC_3, 0x010 */ + u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x014 */ + u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x018 */ + u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x01c */ + u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ + u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ + u32 _rsv1[10]; /* 0x028-04c */ + u32 shaper; /* _SHAPER, 0x050 */ + u32 shaper1; /* _SHAPER_1, 0x054 */ + u32 _rsv2[80]; /* 0x058-194 */ + u32 misc_ctrl; /* _MISC_CTRL, 0x198 */ +}; +check_member(clst_clk_ctlr, misc_ctrl, 0x198); + +/* CC_CCLK_BRST_POL */ +enum { + CC_CCLK_BRST_POL_PLLX_OUT0_LJ = 0x8, +}; + +/* CC_SUPER_CCLK_DIVIDER */ +enum { + CC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 +}; + +/* PLLX_MISC3 */ +enum { + PLLX_IDDQ = 1 << 3, +}; + +/* MISC_CTRL */ +enum { + CLK_SWITCH_MATCH = 1 << 5, +}; + +#define CLK_SWITCH_TIMEOUT_US 1000 +#endif /* _TEGRA210_CLST_CLK_H_ */ diff --git a/src/soc/nvidia/tegra210/include/soc/cpu.h b/src/soc/nvidia/tegra210/include/soc/cpu.h new file mode 100644 index 0000000000..f6ae137ef0 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/cpu.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_CPU_H__ +#define __SOC_NVIDIA_TEGRA210_CPU_H__ + +/* + * Start a core in 64-bit mode at the entry_64 address. Note that entry_64 + * should be a 32-bit address. + */ +void start_cpu(int cpu, void *entry_64); +/* Start CPU wthout any log messages. */ +void start_cpu_silent(int cpu, void *entry_64); +/* Prepare SoC for starting a CPU. Initialize the global state of the SoC. */ +void cpu_prepare_startup(void *entry_64); + +#endif /* __SOC_NVIDIA_TEGRA210_CPU_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/display.h b/src/soc/nvidia/tegra210/include/soc/display.h new file mode 100644 index 0000000000..fdc630ba97 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/display.h @@ -0,0 +1,60 @@ +/* + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_DISPLAY_H__ +#define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_DISPLAY_H__ + +#define COLOR_WHITE 0xFFFFFF +#define COLOR_BLACK 0x000000 + +#define hsync_start(mode) \ + (mode->xres + mode->hfront_porch) + +#define hsync_end(mode) \ + (mode->xres + mode->hfront_porch + mode->hsync_width) + +#define htotal(mode) \ + (mode->xres + mode->hfront_porch + \ + mode->hsync_width + mode->hback_porch) + +#define vtotal(mode) \ + (mode->yres + mode->vfront_porch + \ + mode->vsync_width + mode->vback_porch) + +enum { + /* norrin64 */ + TEGRA_EDID_I2C_ADDRESS = 0x50, +}; + +/* refresh rate = 60/s */ +#define FRAME_IN_MS 17 + +/* forward declaration */ +struct soc_nvidia_tegra210_config; +struct display_controller; + +void dsi_display_startup(device_t dev); +void dp_display_startup(device_t dev); + +int tegra_dc_init(struct display_controller *disp_ctrl); +int update_display_mode(struct display_controller *disp_ctrl, + struct soc_nvidia_tegra210_config *config); +void update_window(const struct soc_nvidia_tegra210_config *config); +void update_display_shift_clock_divider(struct display_controller *disp_ctrl, + u32 shift_clock_div); +void pass_mode_info_to_payload( + struct soc_nvidia_tegra210_config *config); +#endif /* __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h new file mode 100644 index 0000000000..257d529fe9 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/dma.h @@ -0,0 +1,192 @@ +/* + * (C) Copyright 2010-2015 NVIDIA Corporation <www.nvidia.com> + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __NVIDIA_TEGRA210_DMA_H__ +#define __NVIDIA_TEGRA210_DMA_H__ + +#include <inttypes.h> +#include <soc/addressmap.h> + +/* + * The DMA engine operates on 4 bytes at a time, so make sure any data + * passed via DMA is aligned to avoid underrun/overrun. + */ +#define TEGRA_DMA_ALIGN_BYTES 4 + +/* + * Note: Many APB DMA controller registers are laid out such that each + * bit controls or represents the status for the corresponding channel. + * So we will not bother to list each individual bit in this case. + */ +#define APB_COMMAND_GEN (1 << 31) + +#define APB_CNTRL_REG_COUNT_VALUE_MASK 0xffff +#define APB_CNTRL_REG_COUNT_VALUE_SHIFT 0 + +/* + * Note: Many APB DMA controller registers are laid out such that each + * bit controls or represents the status for the corresponding channel. + * So we will not bother to list each individual bit in this case. + */ +#define APB_COMMAND_GEN (1 << 31) + +#define APB_CNTRL_REG_COUNT_VALUE_MASK 0xffff +#define APB_CNTRL_REG_COUNT_VALUE_SHIFT 0 +struct apb_dma { + u32 command; /* 0x00 */ + u32 status; /* 0x04 */ + u32 rsvd1[2]; + u32 cntrl_reg; /* 0x10 */ + u32 irq_sta_cpu; /* 0x14 */ + u32 irq_sta_cop; /* 0x18 */ + u32 irq_mask; /* 0x1c */ + u32 irq_mask_set; /* 0x20 */ + u32 irq_mask_clr; /* 0x24 */ + u32 trig_reg; /* 0x28 */ + u32 channel_trig_reg; /* 0x2c */ + u32 dma_status; /* 0x30 */ + u32 channel_en_reg; /* 0x34 */ + u32 security_reg; /* 0x38 */ + u32 channel_swid; /* 0x3c */ + u32 rsvd[1]; + u32 chan_wt_reg0; /* 0x44 */ + u32 chan_wt_reg1; /* 0x48 */ + u32 chan_wt_reg2; /* 0x4c */ + u32 chan_wr_reg3; /* 0x50 */ + u32 channel_swid1; /* 0x54 */ +} __attribute__((packed)); +check_member(apb_dma, channel_swid1, 0x54); + +/* Security enable for DMA channel */ +#define SECURITY_EN_BIT(ch) (1 << ch) + +/* + * Naming in the doc included a superfluous _CHANNEL_n_ for + * each entry and was left out for the sake of conciseness. + */ +#define APB_CSR_ENB (1 << 31) +#define APB_CSR_IE_EOC (1 << 30) +#define APB_CSR_HOLD (1 << 29) +#define APB_CSR_DIR (1 << 28) +#define APB_CSR_ONCE (1 << 27) +#define APB_CSR_FLOW (1 << 21) +#define APB_CSR_REQ_SEL_MASK 0x1f +#define APB_CSR_REQ_SEL_SHIFT 16 + +enum apbdmachan_req_sel { + APBDMA_SLAVE_CNTR_REQ = 0, + APBDMA_SLAVE_APBIF_CH0 = 1, + APBDMA_SLAVE_APBIF_CH1 = 2, + APBDMA_SLAVE_APBIF_CH2 = 3, + APBDMA_SLAVE_APBIF_CH3 = 4, + APBDMA_SLAVE_QSPI = 5, + APBDMA_SLAVE_APBIF_CH4 = 6, + APBDMA_SLAVE_APBIF_CH5 = 7, + APBDMA_SLAVE_UART_A = 8, + APBDMA_SLAVE_UART_B = 9, + APBDMA_SLAVE_UART_C = 10, + APBDMA_SLAVE_DTV = 11, + APBDMA_SLAVE_APBIF_CH6 = 12, + APBDMA_SLAVE_APBIF_CH7 = 13, + APBDMA_SLAVE_APBIF_CH8 = 14, + APBDMA_SLAVE_SL2B1 = 15, + APBDMA_SLAVE_SL2B2 = 16, + APBDMA_SLAVE_SL2B3 = 17, + APBDMA_SLAVE_SL2B4 = 18, + APBDMA_SLAVE_UART_D = 19, + APBDMA_SLAVE_UART_E = 20, + APBDMA_SLAVE_I2C = 21, + APBDMA_SLAVE_I2C2 = 22, + APBDMA_SLAVE_I2C3 = 23, + APBDMA_SLAVE_DVC_I2C = 24, + APBDMA_SLAVE_OWR = 25, + APBDMA_SLAVE_I2C4 = 26, + APBDMA_SLAVE_SL2B5 = 27, + APBDMA_SLAVE_SL2B6 = 28, + APBDMA_SLAVE_APBIF_CH9 = 29, + APBDMA_SLAVE_I2C6 = 30, + APBDMA_SLAVE_NA31 = 31, +}; + +#define APB_STA_BSY (1 << 31) +#define APB_STA_ISE_EOC (1 << 30) +#define APB_STA_HALT (1 << 29) +#define APB_STA_PING_PONG_STA (1 << 28) +#define APB_STA_DMA_ACTIVITY (1 << 27) +#define APB_STA_CHANNEL_PAUSE (1 << 26) + +#define APB_CSRE_CHANNEL_PAUSE (1 << 31) +#define APB_CSRE_TRIG_SEL_MASK 0x3f +#define APB_CSRE_TRIG_SEL_SHIFT 14 + +#define AHB_PTR_MASK (0x3fffffff) +#define AHB_PTR_SHIFT 2 + +#define AHB_SEQ_INTR_ENB (1 << 31) +#define AHB_BUS_WIDTH_MASK 0x7 +#define AHB_BUS_WIDTH_SHIFT 28 +#define AHB_DATA_SWAP (1 << 27) +#define AHB_BURST_MASK 0x7 +#define AHB_BURST_SHIFT 24 +#define AHB_SEQ_DBL_BUF (1 << 19) +#define AHB_SEQ_WRAP_MASK 0x7 +#define AHB_SEQ_WRAP_SHIFT 16 + +#define APB_PTR_MASK 0x3fffffff +#define APB_PTR_SHIFT 2 + +#define APB_BUS_WIDTH_MASK 0x7 +#define APB_BUS_WIDTH_SHIFT 28 +#define APB_DATA_SWAP (1 << 27) +#define APB_ADDR_WRAP_MASK 0x7 +#define APB_ADDR_WRAP_SHIFT 16 + +#define APB_WORD_TRANSFER_MASK 0x0fffffff +#define APB_WORD_TRANSFER_SHIFT 2 + +struct apb_dma_channel_regs { + u32 csr; /* 0x00 */ + u32 sta; /* 0x04 */ + u32 dma_byte_sta; /* 0x08 */ + u32 csre; /* 0x0c */ + u32 ahb_ptr; /* 0x10 */ + u32 ahb_seq; /* 0x14 */ + u32 apb_ptr; /* 0x18 */ + u32 apb_seq; /* 0x1c */ + u32 wcount; /* 0x20 */ + u32 word_transfer; /* 0x24 */ +} __attribute__((packed)); +check_member(apb_dma_channel_regs, word_transfer, 0x24); + +struct apb_dma_channel { + const int num; + struct apb_dma_channel_regs *regs; + + /* + * Basic high-level semaphore that can be used to "claim" + * a DMA channel e.g. by SPI, I2C, or other peripheral driver. + */ + int in_use; +}; + +struct apb_dma_channel * const dma_claim(void); +void dma_release(struct apb_dma_channel * const channel); +int dma_start(struct apb_dma_channel * const channel); +int dma_stop(struct apb_dma_channel * const channel); +int dma_busy(struct apb_dma_channel * const channel); + +#endif /* __NVIDIA_TEGRA210_DMA_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/emc.h b/src/soc/nvidia/tegra210/include/soc/emc.h new file mode 100644 index 0000000000..b24c14d9a8 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/emc.h @@ -0,0 +1,475 @@ +/* + * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_EMC_H__ +#define __SOC_NVIDIA_TEGRA210_EMC_H__ + +#include <stddef.h> +#include <stdint.h> + +enum { + EMC_PIN_RESET_MASK = 1 << 8, + EMC_PIN_RESET_ACTIVE = 0 << 8, + EMC_PIN_RESET_INACTIVE = 1 << 8, + EMC_PIN_DQM_MASK = 1 << 4, + EMC_PIN_DQM_NORMAL = 0 << 4, + EMC_PIN_DQM_INACTIVE = 1 << 4, + EMC_PIN_CKE_MASK = 1 << 0, + EMC_PIN_CKE_POWERDOWN = 0 << 0, + EMC_PIN_CKE_NORMAL = 1 << 0, + + EMC_REF_CMD_MASK = 1 << 0, + EMC_REF_CMD_REFRESH = 1 << 0, + EMC_REF_NORMAL_MASK = 1 << 1, + EMC_REF_NORMAL_INIT = 0 << 1, + EMC_REF_NORMAL_ENABLED = 1 << 1, + EMC_REF_NUM_SHIFT = 8, + EMC_REF_NUM_MASK = 0xFF << EMC_REF_NUM_SHIFT, + EMC_REF_DEV_SELECTN_SHIFT = 30, + EMC_REF_DEV_SELECTN_MASK = 3 << EMC_REF_DEV_SELECTN_SHIFT, + + EMC_REFCTRL_REF_VALID_MASK = 1 << 31, + EMC_REFCTRL_REF_VALID_DISABLED = 0 << 31, + EMC_REFCTRL_REF_VALID_ENABLED = 1 << 31, + + EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE_MASK = 1 << 1, + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1_MASK = 1 << 2, + EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2_MASK = 1 << 3, + + EMC_NOP_CMD_SHIFT = 0, + EMC_NOP_CMD_MASK = 1 << EMC_NOP_CMD_SHIFT, + EMC_NOP_DEV_SELECTN_SHIFT = 30, + EMC_NOP_DEV_SELECTN_MASK = 3 << EMC_NOP_DEV_SELECTN_SHIFT, + + EMC_TIMING_CONTROL_TIMING_UPDATE = 1, + + EMC_PIN_GPIOEN_SHIFT = 16, + EMC_PIN_GPIO_SHIFT = 12, + EMC_PMACRO_BRICK_CTRL_RFU1_RESET_VAL = 0x1FFF1FFF, + + AUTOCAL_MEASURE_STALL_ENABLE = 1 << 9, + WRITE_MUX_ACTIVE = 1 << 1, + CFG_ADR_EN_LOCKED = 1 << 1, +}; + +struct tegra_emc_regs { + uint32_t intstatus; /* 0x0 */ + uint32_t intmask; /* 0x4 */ + uint32_t dbg; /* 0x8 */ + uint32_t cfg; /* 0xc */ + uint32_t adr_cfg; /* 0x10 */ + uint32_t rsvd_0x14[3]; /* 0x14-0x1C */ + + uint32_t refctrl; /* 0x20 */ + uint32_t pin; /* 0x24 */ + uint32_t timing_control; /* 0x28 */ + uint32_t rc; /* 0x2c */ + uint32_t rfc; /* 0x30 */ + uint32_t ras; /* 0x34 */ + uint32_t rp; /* 0x38 */ + uint32_t r2w; /* 0x3c */ + uint32_t w2r; /* 0x40 */ + uint32_t r2p; /* 0x44 */ + uint32_t w2p; /* 0x48 */ + uint32_t rd_rcd; /* 0x4c */ + uint32_t wr_rcd; /* 0x50 */ + uint32_t rrd; /* 0x54 */ + uint32_t rext; /* 0x58 */ + uint32_t wdv; /* 0x5c */ + uint32_t quse; /* 0x60 */ + uint32_t qrst; /* 0x64 */ + uint32_t qsafe; /* 0x68 */ + uint32_t rdv; /* 0x6c */ + uint32_t refresh; /* 0x70 */ + uint32_t burst_refresh_num; /* 0x74 */ + uint32_t pdex2wr; /* 0x78 */ + uint32_t pdex2rd; /* 0x7c */ + uint32_t pchg2pden; /* 0x80 */ + uint32_t act2pden; /* 0x84 */ + uint32_t ar2pden; /* 0x88 */ + uint32_t rw2pden; /* 0x8c */ + uint32_t txsr; /* 0x90 */ + uint32_t tcke; /* 0x94 */ + uint32_t tfaw; /* 0x98 */ + uint32_t trpab; /* 0x9c */ + uint32_t tclkstable; /* 0xa0 */ + uint32_t tclkstop; /* 0xa4 */ + uint32_t trefbw; /* 0xa8 */ + uint32_t tppd; /* 0xac */ + uint32_t odt_write; /* 0xb0 */ + uint32_t pdex2mrr; /* 0xb4 */ + uint32_t wext; /* 0xb8 */ + uint32_t ctt; /* 0xbc */ + uint32_t rfc_slr; /* 0xc0 */ + uint32_t mrs_wait_cnt2; /* 0xc4 */ + uint32_t mrs_wait_cnt; /* 0xc8 */ + uint32_t mrs; /* 0xcc */ + uint32_t emrs; /* 0xd0 */ + uint32_t ref; /* 0xd4 */ + uint32_t pre; /* 0xd8 */ + uint32_t nop; /* 0xdc */ + uint32_t self_ref; /* 0xe0 */ + uint32_t dpd; /* 0xe4 */ + uint32_t mrw; /* 0xe8 */ + uint32_t mrr; /* 0xec */ + uint32_t cmdq; /* 0xf0 */ + uint32_t mc2emcq; /* 0xf4 */ + uint32_t xm2dqspadctrl3; /* 0xf8 */ + uint32_t rsvd_0xfc[1]; /* 0xfc */ + uint32_t fbio_spare; /* 0x100 */ + uint32_t fbio_cfg5; /* 0x104 */ + uint32_t fbio_wrptr_eq_2; /* 0x108 */ + uint32_t rsvd_0x10c[2]; /* 0x10c-0x110 */ + + uint32_t fbio_cfg6; /* 0x114 */ + uint32_t pdex2cke; /* 0x118 */ + uint32_t cke2pden; /* 0x11C */ + uint32_t cfg_rsv; /* 0x120 */ + uint32_t acpd_control; /* 0x124 */ + uint32_t rsvd_0x128[1]; /* 0x128 */ + uint32_t emrs2; /* 0x12c */ + uint32_t emrs3; /* 0x130 */ + uint32_t mrw2; /* 0x134 */ + uint32_t mrw3; /* 0x138 */ + uint32_t mrw4; /* 0x13c */ + uint32_t clken_override; /* 0x140 */ + uint32_t r2r; /* 0x144 */ + uint32_t w2w; /* 0x148 */ + uint32_t einput; /* 0x14c */ + uint32_t einput_duration; /* 0x150 */ + uint32_t puterm_extra; /* 0x154 */ + uint32_t tckesr; /* 0x158 */ + uint32_t tpd; /* 0x15c */ + uint32_t rsvd_0x160[81]; /* 0x160-0x2A0 */ + + uint32_t auto_cal_config; /* 0x2a4 */ + uint32_t auto_cal_interval; /* 0x2a8 */ + uint32_t auto_cal_status; /* 0x2ac */ + uint32_t req_ctrl; /* 0x2b0 */ + uint32_t status; /* 0x2b4 */ + uint32_t cfg_2; /* 0x2b8 */ + uint32_t cfg_dig_dll; /* 0x2bc */ + uint32_t cfg_dig_dll_period; /* 0x2c0 */ + uint32_t dig_dll_status; /* 0x2C4 */ + uint32_t cfg_dig_dll_1; /* 0x2C8 */ + uint32_t rdv_mask; /* 0x2cc */ + uint32_t wdv_mask; /* 0x2d0 */ + uint32_t rdv_early_mask; /* 0x2d4 */ + uint32_t rdv_early; /* 0x2d8 */ + uint32_t auto_cal_config8; /* 0x2DC */ + uint32_t zcal_interval; /* 0x2e0 */ + uint32_t zcal_wait_cnt; /* 0x2e4 */ + uint32_t zcal_mrw_cmd; /* 0x2e8 */ + uint32_t zq_cal; /* 0x2ec */ + uint32_t xm2cmdpadctrl; /* 0x2f0 */ + uint32_t xm2comppadctrl3; /* 0x2f4 */ + uint32_t auto_cal_vref_sel0; /* 0x2f8 */ + uint32_t xm2dqspadctrl2; /* 0x2fc */ + uint32_t auto_cal_vref_sel1; /* 0x300 */ + uint32_t xm2dqpadctrl2; /* 0x304 */ + uint32_t xm2clkpadctrl; /* 0x308 */ + uint32_t xm2comppadctrl; /* 0x30c */ + uint32_t fdpd_ctrl_dq; /* 0x310 */ + uint32_t fdpd_ctrl_cmd; /* 0x314 */ + uint32_t pmacro_cmd_brick_ctrl_fdpd; /* 0x318 */ + uint32_t pmacro_data_brick_ctrl_fdpd; /* 0x31c */ + uint32_t xm2dqspadctrl4; /* 0x320 */ + uint32_t scratch0; /* 0x324 */ + uint32_t rsvd_0x328[2]; /* 0x328-0x32C */ + + uint32_t pmacro_brick_ctrl_rfu1; /* 0x330 */ + uint32_t pmacro_brick_ctrl_rfu2; /* 0x334 */ + uint32_t rsvd_0x338[18]; /* 0x338-0x37C */ + + uint32_t cmd_mapping_cmd0_0; /* 0x380 */ + uint32_t cmd_mapping_cmd0_1; /* 0x384 */ + uint32_t cmd_mapping_cmd0_2; /* 0x388 */ + uint32_t cmd_mapping_cmd1_0; /* 0x38c */ + uint32_t cmd_mapping_cmd1_1; /* 0x390 */ + uint32_t cmd_mapping_cmd1_2; /* 0x394 */ + uint32_t cmd_mapping_cmd2_0; /* 0x398 */ + uint32_t cmd_mapping_cmd2_1; /* 0x39C */ + uint32_t cmd_mapping_cmd2_2; /* 0x3A0 */ + uint32_t cmd_mapping_cmd3_0; /* 0x3A4 */ + uint32_t cmd_mapping_cmd3_1; /* 0x3A8 */ + uint32_t cmd_mapping_cmd3_2; /* 0x3AC */ + uint32_t cmd_mapping_byte; /* 0x3B0 */ + uint32_t tr_timing_0; /* 0x3B4 */ + uint32_t tr_ctrl_0; /* 0x3B8 */ + uint32_t tr_ctrl_1; /* 0x3BC */ + uint32_t switch_back_ctrl; /* 0x3C0 */ + uint32_t tr_rdv; /* 0x3C4 */ + uint32_t stall_then_exe_before_clkchange; /* 0x3c8 */ + uint32_t stall_then_exe_after_clkchange; /* 0x3cc */ + uint32_t unstall_rw_after_clkchange; /* 0x3d0 */ + uint32_t auto_cal_clk_status; /* 0x3d4 */ + uint32_t sel_dpd_ctrl; /* 0x3d8 */ + uint32_t pre_refresh_req_cnt; /* 0x3dc */ + uint32_t dyn_self_ref_control; /* 0x3e0 */ + uint32_t txsrdll; /* 0x3e4 */ + uint32_t ccfifo_addr; /* 0x3e8 */ + uint32_t ccfifo_data; /* 0x3ec */ + uint32_t ccfifo_status; /* 0x3f0 */ + uint32_t cdb_cntl_1; /* 0x3f4 */ + uint32_t cdb_cntl_2; /* 0x3f8 */ + uint32_t xm2clkpadctrl2; /* 0x3fc */ + uint32_t swizzle_rank0_byte_cfg; /* 0x400 */ + uint32_t swizzle_rank0_byte0; /* 0x404 */ + uint32_t swizzle_rank0_byte1; /* 0x408 */ + uint32_t swizzle_rank0_byte2; /* 0x40c */ + uint32_t swizzle_rank0_byte3; /* 0x410 */ + uint32_t swizzle_rank1_byte_cfg; /* 0x414 */ + uint32_t swizzle_rank1_byte0; /* 0x418 */ + uint32_t swizzle_rank1_byte1; /* 0x41c */ + uint32_t swizzle_rank1_byte2; /* 0x420 */ + uint32_t swizzle_rank1_byte3; /* 0x424 */ + uint32_t issue_qrst; /* 0x428 */ + uint32_t rsvd_0x42C[5]; /* 0x42C-0x43C */ + uint32_t pmc_scratch1; /* 0x440 */ + uint32_t pmc_scratch2; /* 0x444 */ + uint32_t pmc_scratch3; /* 0x448 */ + uint32_t rsvd_0x44C[3]; /* 0x44C-0x454 */ + uint32_t auto_cal_config2; /* 0x458 */ + uint32_t auto_cal_config3; /* 0x45c */ + uint32_t auto_cal_status2; /* 0x460 */ + uint32_t auto_cal_channel; /* 0x464 */ + uint32_t ibdly; /* 0x468 */ + uint32_t obdly; /* 0x46c */ + uint32_t rsvd_0x470[3]; /* 0x470-0x478 */ + + uint32_t dsr_vttgen_drv; /* 0x47c */ + uint32_t txdsrvttgen; /* 0x480 */ + uint32_t xm2cmdpadctrl4; /* 0x484 */ + uint32_t xm2cmdpadctrl5; /* 0x488 */ + uint32_t we_duration; /* 0x48C */ + uint32_t ws_duration; /* 0x490 */ + uint32_t wev; /* 0x494 */ + uint32_t wsv; /* 0x498 */ + uint32_t cfg_3; /* 0x49C */ + uint32_t mrw5; /* 0x4A0 */ + uint32_t mrw6; /* 0x4A4 */ + uint32_t mrw7; /* 0x4A8 */ + uint32_t mrw8; /* 0x4AC */ + uint32_t mrw9; /* 0x4B0 */ + uint32_t mrw10; /* 0x4B4 */ + uint32_t mrw11; /* 0x4B8 */ + uint32_t mrw12; /* 0x4BC */ + uint32_t mrw13; /* 0x4C0 */ + uint32_t mrw14; /* 0x4C4 */ + uint32_t rsvd_0x4c8[2]; /* 0x4C8-0x4CC */ + + uint32_t mrw15; /* 0x4D0 */ + uint32_t cfg_sync; /* 0x4D4 */ + uint32_t fdpd_ctrl_cmd_no_ramp; /* 0x4D8 */ + uint32_t rsvd_0x4dc[1]; /* 0x4DC */ + uint32_t wdv_chk; /* 0x4E0 */ + uint32_t rsvd_0x4e4[28]; /* 0x4E4-0x550 */ + + uint32_t cfg_pipe2; /* 0x554 */ + uint32_t cfg_pipe_clk; /* 0x558 */ + uint32_t cfg_pipe1; /* 0x55C */ + uint32_t cfg_pipe; /* 0x560 */ + uint32_t qpop; /* 0x564 */ + uint32_t quse_width; /* 0x568 */ + uint32_t puterm_width; /* 0x56c */ + uint32_t bgbias_ctl0; /* 0x570 */ + uint32_t auto_cal_config7; /* 0x574 */ + uint32_t xm2comppadctrl2; /* 0x578 */ + uint32_t comppadswctrl; /* 0x57C */ + uint32_t refctrl2; /* 0x580 */ + uint32_t fbio_cfg7; /* 0x584 */ + uint32_t data_brlshft_0; /* 0x588 */ + uint32_t data_brlshft_1; /* 0x58C */ + uint32_t rfcpb; /* 0x590 */ + uint32_t dqs_brlshft_0; /* 0x594 */ + uint32_t dqs_brlshft_1; /* 0x598 */ + uint32_t cmd_brlshft_0; /* 0x59C */ + uint32_t cmd_brlshft_1; /* 0x5A0 */ + uint32_t cmd_brlshft_2; /* 0x5A4 */ + uint32_t cmd_brlshft_3; /* 0x5A8 */ + uint32_t quse_brlshft_0; /* 0x5AC */ + uint32_t auto_cal_config4; /* 0x5B0 */ + uint32_t auto_cal_config5; /* 0x5B4 */ + uint32_t quse_brlshft_1; /* 0x5B8 */ + uint32_t quse_brlshft_2; /* 0x5BC */ + uint32_t ccdmw; /* 0x5C0 */ + uint32_t quse_brlshft_3; /* 0x5C4 */ + uint32_t fbio_cfg8; /* 0x5C8 */ + uint32_t auto_cal_config6; /* 0x5CC */ + uint32_t protobist_config_addr_1; /* 0x5D0 */ + uint32_t protobist_config_addr_2; /* 0x5D4 */ + uint32_t protobist_misc; /* 0x5D8 */ + uint32_t protobist_wdata_lower; /* 0x5DC */ + uint32_t protobist_wdata_upper; /* 0x5E0 */ + uint32_t dll_cfg0; /* 0x5E4 */ + uint32_t dll_cfg1; /* 0x5E8 */ + uint32_t protobist_rdata; /* 0x5EC */ + uint32_t config_sample_delay; /* 0x5F0 */ + uint32_t cfg_update; /* 0x5F4 */ + uint32_t rsvd_0x5f8[2]; /* 0x5F8-0x5FC */ + + uint32_t pmacro_quse_ddll_rank0_0; /* 0x600 */ + uint32_t pmacro_quse_ddll_rank0_1; /* 0x604 */ + uint32_t pmacro_quse_ddll_rank0_2; /* 0x608 */ + uint32_t pmacro_quse_ddll_rank0_3; /* 0x60C */ + uint32_t pmacro_quse_ddll_rank0_4; /* 0x610 */ + uint32_t pmacro_quse_ddll_rank0_5; /* 0x614 */ + uint32_t rsvd_0x618[2]; /* 0x618-0x61C */ + + uint32_t pmacro_quse_ddll_rank1_0; /* 0x620 */ + uint32_t pmacro_quse_ddll_rank1_1; /* 0x624 */ + uint32_t pmacro_quse_ddll_rank1_2; /* 0x628 */ + uint32_t pmacro_quse_ddll_rank1_3; /* 0x62C */ + uint32_t pmacro_quse_ddll_rank1_4; /* 0x630 */ + uint32_t pmacro_quse_ddll_rank1_5; /* 0x634 */ + uint32_t rsvd_0x638[2]; /* 0x638-0x63C */ + + uint32_t pmacro_ob_ddll_long_dq_rank0_0; /* 0x640 */ + uint32_t pmacro_ob_ddll_long_dq_rank0_1; /* 0x644 */ + uint32_t pmacro_ob_ddll_long_dq_rank0_2; /* 0x648 */ + uint32_t pmacro_ob_ddll_long_dq_rank0_3; /* 0x64C */ + uint32_t pmacro_ob_ddll_long_dq_rank0_4; /* 0x650 */ + uint32_t pmacro_ob_ddll_long_dq_rank0_5; /* 0x654 */ + uint32_t rsvd_0x658[2]; /* 0x658-0x65C */ + + uint32_t pmacro_ob_ddll_long_dq_rank1_0; /* 0x660 */ + uint32_t pmacro_ob_ddll_long_dq_rank1_1; /* 0x664 */ + uint32_t pmacro_ob_ddll_long_dq_rank1_2; /* 0x668 */ + uint32_t pmacro_ob_ddll_long_dq_rank1_3; /* 0x66C */ + uint32_t pmacro_ob_ddll_long_dq_rank1_4; /* 0x670 */ + uint32_t pmacro_ob_ddll_long_dq_rank1_5; /* 0x674 */ + uint32_t rsvd_0x678[2]; /* 0x678-0x67C */ + + uint32_t pmacro_ob_ddll_long_dqs_rank0_0; /* 0x680 */ + uint32_t pmacro_ob_ddll_long_dqs_rank0_1; /* 0x684 */ + uint32_t pmacro_ob_ddll_long_dqs_rank0_2; /* 0x688 */ + uint32_t pmacro_ob_ddll_long_dqs_rank0_3; /* 0x68C */ + uint32_t pmacro_ob_ddll_long_dqs_rank0_4; /* 0x690 */ + uint32_t pmacro_ob_ddll_long_dqs_rank0_5; /* 0x694 */ + uint32_t rsvd_0x698[2]; /* 0x698-0x69C */ + + uint32_t pmacro_ob_ddll_long_dqs_rank1_0; /* 0x6A0 */ + uint32_t pmacro_ob_ddll_long_dqs_rank1_1; /* 0x6A4 */ + uint32_t pmacro_ob_ddll_long_dqs_rank1_2; /* 0x6A8 */ + uint32_t pmacro_ob_ddll_long_dqs_rank1_3; /* 0x6AC */ + uint32_t pmacro_ob_ddll_long_dqs_rank1_4; /* 0x6B0 */ + uint32_t pmacro_ob_ddll_long_dqs_rank1_5; /* 0x6B4 */ + uint32_t rsvd_0x6B8[2]; /* 0x6B8-0x6BC */ + + uint32_t pmacro_ib_ddll_long_dqs_rank0_0; /* 0x6C0 */ + uint32_t pmacro_ib_ddll_long_dqs_rank0_1; /* 0x6C4 */ + uint32_t pmacro_ib_ddll_long_dqs_rank0_2; /* 0x6C8 */ + uint32_t pmacro_ib_ddll_long_dqs_rank0_3; /* 0x6CC */ + uint32_t pmacro_ib_ddll_long_dqs_rank0_4; /* 0x6D0 */ + uint32_t pmacro_ib_ddll_long_dqs_rank0_5; /* 0x6D4 */ + uint32_t rsvd_0x6D8[2]; /* 0x6D8-0x6DC */ + + uint32_t pmacro_ib_ddll_long_dqs_rank1_0; /* 0x6E0 */ + uint32_t pmacro_ib_ddll_long_dqs_rank1_1; /* 0x6E4 */ + uint32_t pmacro_ib_ddll_long_dqs_rank1_2; /* 0x6E8 */ + uint32_t pmacro_ib_ddll_long_dqs_rank1_3; /* 0x6EC */ + uint32_t pmacro_ib_ddll_long_dqs_rank1_4; /* 0x6F0 */ + uint32_t pmacro_ib_ddll_long_dqs_rank1_5; /* 0x6F4 */ + uint32_t rsvd_0x6F8[2]; /* 0x6F8-0x6FC */ + + uint32_t pmacro_autocal_cfg0; /* 0x700 */ + uint32_t pmacro_autocal_cfg1; /* 0x704 */ + uint32_t pmacro_autocal_cfg2; /* 0x708 */ + uint32_t rsvd_0x70C[5]; /* 0x70C-0x71C */ + + uint32_t pmacro_tx_pwrd_0; /* 0x720 */ + uint32_t pmacro_tx_pwrd_1; /* 0x724 */ + uint32_t pmacro_tx_pwrd_2; /* 0x728 */ + uint32_t pmacro_tx_pwrd_3; /* 0x72C */ + uint32_t pmacro_tx_pwrd_4; /* 0x730 */ + uint32_t pmacro_tx_pwrd_5; /* 0x734 */ + uint32_t rsvd_0x738[2]; /* 0x738-0x73C */ + + uint32_t pmacro_tx_sel_clk_src_0; /* 0x740 */ + uint32_t pmacro_tx_sel_clk_src_1; /* 0x744 */ + uint32_t pmacro_tx_sel_clk_src_2; /* 0x748 */ + uint32_t pmacro_tx_sel_clk_src_3; /* 0x74C */ + uint32_t pmacro_tx_sel_clk_src_4; /* 0x750 */ + uint32_t pmacro_tx_sel_clk_src_5; /* 0x754 */ + uint32_t rsvd_0x758[2]; /* 0x758-0x75C */ + + uint32_t pmacro_ddll_bypass; /* 0x760 */ + uint32_t rsvd_0x764[3]; /* 0x764-0x76C */ + + uint32_t pmacro_ddll_pwrd_0; /* 0x770 */ + uint32_t pmacro_ddll_pwrd_1; /* 0x774 */ + uint32_t pmacro_ddll_pwrd_2; /* 0x778 */ + uint32_t rsvd_0x77C[1]; /* 0x77C */ + uint32_t pmacro_cmd_ctrl_0; /* 0x780 */ + uint32_t pmacro_cmd_ctrl_1; /* 0x784 */ + uint32_t pmacro_cmd_ctrl_2; /* 0x788 */ + uint32_t rsvd_0x78C[277]; /* 0x78C-0xBDC */ + + uint32_t pmacro_ib_vref_dq_0; /* 0xBE0 */ + uint32_t pmacro_ib_vref_dq_1; /* 0xBE4 */ + uint32_t pmacro_ib_vref_dq_2; /* 0xBE8 */ + uint32_t rsvd_0xBEC[1]; /* 0xBEC */ + uint32_t pmacro_ib_vref_dqs_0; /* 0xBF0 */ + uint32_t pmacro_ib_vref_dqs_1; /* 0xBF4 */ + uint32_t pmacro_ib_vref_dqs_2; /* 0xBF8 */ + uint32_t rsvd_0xBFC[1]; /* 0xBFC */ + uint32_t pmacro_ddll_long_cmd_0; /* 0xC00 */ + uint32_t pmacro_ddll_long_cmd_1; /* 0xC04 */ + uint32_t pmacro_ddll_long_cmd_2; /* 0xC08 */ + uint32_t pmacro_ddll_long_cmd_3; /* 0xC0C */ + uint32_t pmacro_ddll_long_cmd_4; /* 0xC10 */ + uint32_t pmacro_ddll_long_cmd_5; /* 0xC14 */ + uint32_t rsvd_0xC18[2]; /* 0xC18-0xC1C */ + + uint32_t pmacro_ddll_short_cmd_0; /* 0xC20 */ + uint32_t pmacro_ddll_short_cmd_1; /* 0xC24 */ + uint32_t pmacro_ddll_short_cmd_2; /* 0xC28 */ + uint32_t rsvd_0xC2C[2]; /* 0xC2C-0xC30 */ + + uint32_t pmacro_vttgen_ctrl0; /* 0xC34 */ + uint32_t pmacro_vttgen_ctrl1; /* 0xC38 */ + uint32_t pmacro_bg_bias_ctrl_0; /* 0xC3C */ + uint32_t pmacro_pad_cfg_ctrl; /* 0xC40 */ + uint32_t pmacro_zctrl; /* 0xC44 */ + uint32_t pmacro_rx_term; /* 0xC48 */ + uint32_t pmacro_cmd_tx_drv; /* 0xC4C */ + uint32_t pmacro_cmd_pad_rx_ctrl; /* 0xC50 */ + uint32_t pmacro_data_pad_rx_ctrl; /* 0xC54 */ + uint32_t pmacro_cmd_rx_term_mode; /* 0xC58 */ + uint32_t pmacro_data_rx_term_mode; /* 0xC5C */ + uint32_t pmacro_cmd_pad_tx_ctrl; /* 0xC60 */ + uint32_t pmacro_data_pad_tx_ctrl; /* 0xC64 */ + uint32_t pmacro_common_pad_tx_ctrl; /* 0xC68 */ + uint32_t rsvd_0xC6C[1]; /* 0xC6C */ + uint32_t pmacro_dq_tx_drv; /* 0xC70 */ + uint32_t pmacro_ca_tx_drv; /* 0xC74 */ + uint32_t pmacro_autocal_cfg_common; /* 0xC78 */ + uint32_t rsvd_0xC7C[1]; /* 0xC7C */ + uint32_t pmacro_brick_mapping0; /* 0xC80 */ + uint32_t pmacro_brick_mapping1; /* 0xC84 */ + uint32_t pmacro_brick_mapping2; /* 0xC88 */ + uint32_t rsvd_0xC8C[25]; /* 0xC8C-0xCEC */ + + uint32_t pmacro_vttgen_ctrl2; /* 0xCF0 */ + uint32_t pmacro_ib_rxrt; /* 0xCF4 */ + uint32_t pmacro_training_ctrl0; /* 0xCF8 */ + uint32_t pmacro_training_ctrl1; /* 0xCFC */ +} __attribute__((packed)); + +check_member(tegra_emc_regs, pmacro_training_ctrl1, 0xCFC); + +#endif /* __SOC_NVIDIA_TEGRA210_EMC_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/flow.h b/src/soc/nvidia/tegra210/include/soc/flow.h new file mode 100644 index 0000000000..a3eccf868b --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/flow.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA210_FLOW_H_ +#define _TEGRA210_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ + u32 flow_dbg_sel; /* offset 0x44 */ + u32 flow_dbg_cnt0; /* offset 0x48 */ + u32 flow_dbg_cnt1; /* offset 0x4c */ + u32 flow_dbg_qual; /* offset 0x50 */ + u32 flow_ctlr_spare; /* offset 0x54 */ + u32 reserved; /* offset 0x58 */ + u32 fc_seq_intercept; /* offset 0x5c */ +}; +check_member(flow_ctlr, fc_seq_intercept, 0x5c); + +enum { + FLOW_MODE_SHIFT = 29, + FLOW_MODE_MASK = 0x7 << FLOW_MODE_SHIFT, + + FLOW_MODE_NONE = 0 << FLOW_MODE_SHIFT, + FLOW_MODE_RUN_AND_INT = 1 << FLOW_MODE_SHIFT, + FLOW_MODE_WAITEVENT = 2 << FLOW_MODE_SHIFT, + FLOW_MODE_WAITEVENT_AND_INT = 3 << FLOW_MODE_SHIFT, + FLOW_MODE_STOP_UNTIL_IRQ = 4 << FLOW_MODE_SHIFT, + FLOW_MODE_STOP_UNTIL_IRQ_AND_INT = 5 << FLOW_MODE_SHIFT, + FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ = 6 << FLOW_MODE_SHIFT, +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +enum { + FLOW_EVENT_GIC_FIQ = 1 << 8, + FLOW_EVENT_GIC_IRQ = 1 << 9, + FLOW_EVENT_LIC_FIQ = 1 << 10, + FLOW_EVENT_LIC_IRQ = 1 << 11, + FLOW_EVENT_IBF = 1 << 12, + FLOW_EVENT_IBE = 1 << 13, + FLOW_EVENT_OBF = 1 << 14, + FLOW_EVENT_OBE = 1 << 15, + FLOW_EVENT_XRQ_A = 1 << 16, + FLOW_EVENT_XRQ_B = 1 << 17, + FLOW_EVENT_XRQ_C = 1 << 18, + FLOW_EVENT_XRQ_D = 1 << 19, + FLOW_EVENT_SMP30 = 1 << 20, + FLOW_EVENT_SMP31 = 1 << 21, + FLOW_EVENT_X_RDY = 1 << 22, + FLOW_EVENT_SEC = 1 << 23, + FLOW_EVENT_MSEC = 1 << 24, + FLOW_EVENT_USEC = 1 << 25, + FLOW_EVENT_X32K = 1 << 26, + FLOW_EVENT_SCLK = 1 << 27, + FLOW_EVENT_JTAG = 1 << 28 +}; + +#endif /* _TEGRA210_FLOW_H_ */ diff --git a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h new file mode 100644 index 0000000000..47d68b0651 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _TEGRA210_FLOW_CTRL_H_ +#define _TEGRA210_FLOW_CTRL_H_ + +void flowctrl_cpu_off(int cpu); +void flowctrl_cpu_on(int cpu); +void flowctrl_cpu_suspend(int cpu); +void flowctrl_write_cc4_ctrl(int cpu, uint32_t val); +void flowctrl_write_cpu_csr(int cpu, uint32_t val); +void flowctrl_write_cpu_halt(int cpu, uint32_t val); + +#endif diff --git a/src/soc/nvidia/tegra210/include/soc/funitcfg.h b/src/soc/nvidia/tegra210/include/soc/funitcfg.h new file mode 100644 index 0000000000..d51b13fe22 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/funitcfg.h @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_FUNIT_CFG_H +#define __SOC_NVIDIA_TEGRA210_FUNIT_CFG_H + +#include <soc/clock.h> +#include <soc/padconfig.h> +#include <soc/pinmux.h> +#include <stdint.h> + +#define FUNIT_INDEX(_name) FUNIT_##_name + +enum { + FUNIT_INDEX(I2C1), + FUNIT_INDEX(I2C2), + FUNIT_INDEX(I2C3), + FUNIT_INDEX(I2C5), + FUNIT_INDEX(I2C6), + FUNIT_INDEX(SDMMC1), + FUNIT_INDEX(SDMMC4), + FUNIT_INDEX(USBD), + FUNIT_INDEX(USB2), + FUNIT_INDEX(QSPI), + FUNIT_INDEX(I2S1), + FUNIT_INDEX_MAX, +}; + +/* + * Note: these bus numbers are dependent on the driver implementations, and + * currently the I2C is 0-based and SPI is 1-based in its indexing. + */ +enum { + + I2C1_BUS = 0, + I2C2_BUS = 1, + I2C3_BUS = 2, + I2C5_BUS = 4, + I2CPWR_BUS = I2C5_BUS, + I2C6_BUS = 5, + QSPI_BUS = 7, + + SPI1_BUS = 1, + SPI4_BUS = 4, +}; + +struct funit_cfg { + uint32_t funit_index; + uint32_t clk_src_id; + uint32_t clk_src_freq_id; + uint32_t clk_dev_freq_khz; + struct pad_config const* pad_cfg; + size_t pad_cfg_size; +}; + +#define FUNIT_CFG(_funit,_clk_src,_clk_freq,_cfg,_cfg_size) \ + { \ + .funit_index = FUNIT_INDEX(_funit), \ + .clk_src_id = CLK_SRC_DEV_ID(_funit, _clk_src), \ + .clk_src_freq_id = CLK_SRC_FREQ_ID(_funit, _clk_src), \ + .clk_dev_freq_khz = _clk_freq, \ + .pad_cfg = _cfg, \ + .pad_cfg_size = _cfg_size, \ + } + +#define FUNIT_CFG_USB(_funit) \ + { \ + .funit_index = FUNIT_INDEX(_funit), \ + .pad_cfg = NULL, \ + .pad_cfg_size = 0, \ + } + +/* + * Configure the funits associated with entry according to the configuration. + */ +void soc_configure_funits(const struct funit_cfg * const entries, size_t num); + +#endif /* __SOC_NVIDIA_TEGRA210_FUNIT_CFG_H */ diff --git a/src/soc/nvidia/tegra210/include/soc/gpio.h b/src/soc/nvidia/tegra210/include/soc/gpio.h new file mode 100644 index 0000000000..f4c236a99f --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/gpio.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_GPIO_H__ +#define __SOC_NVIDIA_TEGRA210_GPIO_H__ + +#include <soc/pinmux.h> + +#endif /* __SOC_NVIDIA_TEGRA210_GPIO_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/id.h b/src/soc/nvidia/tegra210/include/soc/id.h new file mode 100644 index 0000000000..5090a31081 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/id.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ +#define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ + + +#include <arch/io.h> +#include <soc/addressmap.h> + +static inline int context_avp(void) +{ + const uint32_t avp_id = 0xaaaaaaaa; + void * const uptag = (void *)(uintptr_t)TEGRA_PG_UP_BASE; + + return read32(uptag) == avp_id; +} + +#endif /* define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_ID_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/maincpu.h b/src/soc/nvidia/tegra210/include/soc/maincpu.h new file mode 100644 index 0000000000..813caba82c --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/maincpu.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_MAINCPU_H__ +#define __SOC_NVIDIA_TEGRA210_MAINCPU_H__ + +#include <stdint.h> + +extern u32 maincpu_stack_pointer; +extern u32 maincpu_entry_point; +void maincpu_setup(void); + +#endif /* __SOC_NVIDIA_TEGRA210_MAINCPU_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/mc.h b/src/soc/nvidia/tegra210/include/soc/mc.h new file mode 100644 index 0000000000..51ae827b93 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/mc.h @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_MC_H__ +#define __SOC_NVIDIA_TEGRA210_MC_H__ + +#include <stddef.h> +#include <stdint.h> + +// Memory Controller registers we need/care about + +struct tegra_mc_regs { + uint32_t rsvd_0x0[4]; /* 0x00 */ + uint32_t smmu_config; /* 0x10 */ + uint32_t smmu_tlb_config; /* 0x14 */ + uint32_t smmu_ptc_config; /* 0x18 */ + uint32_t smmu_ptb_asid; /* 0x1c */ + uint32_t smmu_ptb_data; /* 0x20 */ + uint32_t rsvd_0x24[3]; /* 0x24 */ + uint32_t smmu_tlb_flush; /* 0x30 */ + uint32_t smmu_ptc_flush; /* 0x34 */ + uint32_t rsvd_0x38[6]; /* 0x38 */ + uint32_t emem_cfg; /* 0x50 */ + uint32_t emem_adr_cfg; /* 0x54 */ + uint32_t emem_adr_cfg_dev0; /* 0x58 */ + uint32_t emem_adr_cfg_dev1; /* 0x5c */ + uint32_t emem_adr_cfg_channel_mask; /* 0x60 */ + uint32_t emem_adr_cfg_bank_mask_0; /* 0x64 */ + uint32_t emem_adr_cfg_bank_mask_1; /* 0x68 */ + uint32_t emem_adr_cfg_bank_mask_2; /* 0x6c */ + uint32_t security_cfg0; /* 0x70 */ + uint32_t security_cfg1; /* 0x74 */ + uint32_t rsvd_0x78[6]; /* 0x78 */ + uint32_t emem_arb_cfg; /* 0x90 */ + uint32_t emem_arb_outstanding_req; /* 0x94 */ + uint32_t emem_arb_timing_rcd; /* 0x98 */ + uint32_t emem_arb_timing_rp; /* 0x9c */ + uint32_t emem_arb_timing_rc; /* 0xa0 */ + uint32_t emem_arb_timing_ras; /* 0xa4 */ + uint32_t emem_arb_timing_faw; /* 0xa8 */ + uint32_t emem_arb_timing_rrd; /* 0xac */ + uint32_t emem_arb_timing_rap2pre; /* 0xb0 */ + uint32_t emem_arb_timing_wap2pre; /* 0xb4 */ + uint32_t emem_arb_timing_r2r; /* 0xb8 */ + uint32_t emem_arb_timing_w2w; /* 0xbc */ + uint32_t emem_arb_timing_r2w; /* 0xc0 */ + uint32_t emem_arb_timing_w2r; /* 0xc4 */ + uint32_t emem_arb_misc2; /* 0xC8 */ + uint32_t rsvd_0xcc[1]; /* 0xCC */ + uint32_t emem_arb_da_turns; /* 0xd0 */ + uint32_t emem_arb_da_covers; /* 0xd4 */ + uint32_t emem_arb_misc0; /* 0xd8 */ + uint32_t emem_arb_misc1; /* 0xdc */ + uint32_t emem_arb_ring1_throttle; /* 0xe0 */ + uint32_t emem_arb_ring3_throttle; /* 0xe4 */ + uint32_t emem_arb_override; /* 0xe8 */ + uint32_t emem_arb_rsv; /* 0xec */ + uint32_t rsvd_0xf0[1]; /* 0xf0 */ + uint32_t clken_override; /* 0xf4 */ + uint32_t timing_control_dbg; /* 0xf8 */ + uint32_t timing_control; /* 0xfc */ + uint32_t stat_control; /* 0x100 */ + uint32_t rsvd_0x104[65]; /* 0x104 */ + uint32_t emem_arb_isochronous_0; /* 0x208 */ + uint32_t emem_arb_isochronous_1; /* 0x20c */ + uint32_t emem_arb_isochronous_2; /* 0x210 */ + uint32_t rsvd_0x214[38]; /* 0x214 */ + uint32_t dis_extra_snap_levels; /* 0x2ac */ + uint32_t rsvd_0x2b0[90]; /* 0x2b0 */ + uint32_t video_protect_vpr_override; /* 0x418 */ + uint32_t rsvd_0x41c[93]; /* 0x41c */ + uint32_t video_protect_vpr_override1; /* 0x590 */ + uint32_t rsvd_0x594[29]; /* 0x594 */ + uint32_t display_snap_ring; /* 0x608 */ + uint32_t rsvd_0x60c[15]; /* 0x60c */ + uint32_t video_protect_bom; /* 0x648 */ + uint32_t video_protect_size_mb; /* 0x64c */ + uint32_t video_protect_reg_ctrl; /* 0x650 */ + uint32_t rsvd_0x654[4]; /* 0x654 */ + uint32_t emem_cfg_access_ctrl; /* 0x664 */ + uint32_t rsvd_0x668[2]; /* 0x668 */ + uint32_t sec_carveout_bom; /* 0x670 */ + uint32_t sec_carveout_size_mb; /* 0x674 */ + uint32_t sec_carveout_reg_ctrl; /* 0x678 */ + uint32_t rsvd_0x67c[17]; /* 0x67C-0x6BC */ + + uint32_t emem_arb_timing_rfcpb; /* 0x6C0 */ + uint32_t emem_arb_timing_ccdmw; /* 0x6C4 */ + uint32_t rsvd_0x6c8[10]; /* 0x6C8-0x6EC */ + + uint32_t emem_arb_refpb_hp_ctrl; /* 0x6F0 */ + uint32_t emem_arb_refpb_bank_ctrl; /* 0x6F4 */ + uint32_t rsvd_0x6f8[156]; /* 0x6F8-0x964 */ + + uint32_t emem_arb_override_1; /* 0x968 */ + uint32_t rsvd_0x96c[3]; /* 0x96c */ + uint32_t video_protect_bom_adr_hi; /* 0x978 */ + uint32_t rsvd_0x97c[2]; /* 0x97c */ + uint32_t video_protect_gpu_override_0; /* 0x984 */ + uint32_t video_protect_gpu_override_1; /* 0x988 */ + uint32_t rsvd_0x98c[5]; /* 0x98c */ + uint32_t mts_carveout_bom; /* 0x9a0 */ + uint32_t mts_carveout_size_mb; /* 0x9a4 */ + uint32_t mts_carveout_adr_hi; /* 0x9a8 */ + uint32_t mts_carveout_reg_ctrl; /* 0x9ac */ + uint32_t rsvd_0x9b0[4]; /* 0x9b0 */ + uint32_t emem_bank_swizzle_cfg0; /* 0x9c0 */ + uint32_t emem_bank_swizzle_cfg1; /* 0x9c4 */ + uint32_t emem_bank_swizzle_cfg2; /* 0x9c8 */ + uint32_t emem_bank_swizzle_cfg3; /* 0x9cc */ + uint32_t rsvd_0x9d0[1]; /* 0x9d0 */ + uint32_t sec_carveout_adr_hi; /* 0x9d4 */ + uint32_t rsvd_0x9d8; /* 0x9D8 */ + uint32_t da_config0; /* 0x9DC */ + uint32_t rsvd_0x9c0[138]; /* 0x9E0-0xc04 */ + + uint32_t security_carveout1_cfg0; /* 0xc08 */ + uint32_t security_carveout1_bom; /* 0xc0c */ + uint32_t security_carveout1_bom_hi; /* 0xc10 */ + uint32_t security_carveout1_size_128kb; /* 0xc14 */ + uint32_t security_carveout1_ca0; /* 0xc18 */ + uint32_t security_carveout1_ca1; /* 0xc1c */ + uint32_t security_carveout1_ca2; /* 0xc20 */ + uint32_t security_carveout1_ca3; /* 0xc24 */ + uint32_t security_carveout1_ca4; /* 0xc28 */ + uint32_t security_carveout1_cfia0; /* 0xc2c */ + uint32_t security_carveout1_cfia1; /* 0xc30 */ + uint32_t security_carveout1_cfia2; /* 0xc34 */ + uint32_t security_carveout1_cfia3; /* 0xc38 */ + uint32_t security_carveout1_cfia4; /* 0xc3c */ + uint32_t rsvd_0xc40[6]; /* 0xc40-0xc54 */ + + uint32_t security_carveout2_cfg0; /* 0xc58 */ + uint32_t security_carveout2_bom; /* 0xc5c */ + uint32_t security_carveout2_bom_hi; /* 0xc60 */ + uint32_t security_carveout2_size_128kb; /* 0xc64 */ + uint32_t security_carveout2_ca0; /* 0xc68 */ + uint32_t security_carveout2_ca1; /* 0xc6c */ + uint32_t security_carveout2_ca2; /* 0xc70 */ + uint32_t security_carveout2_ca3; /* 0xc74 */ + uint32_t security_carveout2_ca4; /* 0xc78 */ + uint32_t security_carveout2_cfia0; /* 0xc7c */ + uint32_t security_carveout2_cfia1; /* 0xc80 */ + uint32_t security_carveout2_cfia2; /* 0xc84 */ + uint32_t security_carveout2_cfia3; /* 0xc88 */ + uint32_t security_carveout2_cfia4; /* 0xc8c */ + uint32_t rsvd_0xc90[6]; /* 0xc90-0xca4 */ + + uint32_t security_carveout3_cfg0; /* 0xca8 */ + uint32_t security_carveout3_bom; /* 0xcac */ + uint32_t security_carveout3_bom_hi; /* 0xcb0 */ + uint32_t security_carveout3_size_128kb; /* 0xcb4 */ + uint32_t security_carveout3_ca0; /* 0xcb8 */ + uint32_t security_carveout3_ca1; /* 0xcbc */ + uint32_t security_carveout3_ca2; /* 0xcc0 */ + uint32_t security_carveout3_ca3; /* 0xcc4 */ + uint32_t security_carveout3_ca4; /* 0xcc8 */ + uint32_t security_carveout3_cfia0; /* 0xccc */ + uint32_t security_carveout3_cfia1; /* 0xcd0 */ + uint32_t security_carveout3_cfia2; /* 0xcd4 */ + uint32_t security_carveout3_cfia3; /* 0xcd8 */ + uint32_t security_carveout3_cfia4; /* 0xcdc */ + uint32_t rsvd_0xce0[6]; /* 0xce0-0xcf4 */ + + uint32_t security_carveout4_cfg0; /* 0xcf8 */ + uint32_t security_carveout4_bom; /* 0xcfc */ + uint32_t security_carveout4_bom_hi; /* 0xd00 */ + uint32_t security_carveout4_size_128kb; /* 0xd04 */ + uint32_t security_carveout4_ca0; /* 0xd08 */ + uint32_t security_carveout4_ca1; /* 0xd0c */ + uint32_t security_carveout4_ca2; /* 0xd10 */ + uint32_t security_carveout4_ca3; /* 0xd14 */ + uint32_t security_carveout4_ca4; /* 0xd18 */ + uint32_t security_carveout4_cfia0; /* 0xd1c */ + uint32_t security_carveout4_cfia1; /* 0xd20 */ + uint32_t security_carveout4_cfia2; /* 0xd24 */ + uint32_t security_carveout4_cfia3; /* 0xd28 */ + uint32_t security_carveout4_cfia4; /* 0xd2c */ + uint32_t rsvd_0xd30[6]; /* 0xd30-0xd44 */ + + uint32_t security_carveout5_cfg0; /* 0xd48 */ + uint32_t security_carveout5_bom; /* 0xd4c */ + uint32_t security_carveout5_bom_hi; /* 0xd50 */ + uint32_t security_carveout5_size_128kb; /* 0xd54 */ + uint32_t security_carveout5_ca0; /* 0xd58 */ + uint32_t security_carveout5_ca1; /* 0xd5c */ + uint32_t security_carveout5_ca2; /* 0xd60 */ + uint32_t security_carveout5_ca3; /* 0xd64 */ + uint32_t security_carveout5_ca4; /* 0xd68 */ + uint32_t security_carveout5_cfia0; /* 0xd6c */ + uint32_t security_carveout5_cfia1; /* 0xd70 */ + uint32_t security_carveout5_cfia2; /* 0xd74 */ + uint32_t security_carveout5_cfia3; /* 0xd78 */ + uint32_t security_carveout5_cfia4; /* 0xd7c */ +}; + +enum { + MC_SMMU_CONFIG_ENABLE = 1, + + MC_EMEM_CFG_SIZE_MB_SHIFT = 0, + MC_EMEM_CFG_SIZE_MB_MASK = 0x3fff, + + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_SHIFT = 27, + MC_EMEM_ARB_MISC0_MC_EMC_SAME_FREQ_MASK = 1 << 27, + + MC_EMEM_CFG_ACCESS_CTRL_WRITE_ACCESS_DISABLED = 1, + + MC_TIMING_CONTROL_TIMING_UPDATE = 1, +}; + +#define MC_SECURITY_CARVEOUT_LOCKED (1 << 1) +#define MC_VPR_WR_ACCESS_DISABLE (1 << 0) +#define MC_VPR_ALLOW_TZ_WR_ACCESS_ENABLE (1 << 1) + +check_member(tegra_mc_regs, security_carveout5_cfia4, 0xd7c); + +#endif /* __SOC_NVIDIA_TEGRA210_MC_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld new file mode 100644 index 0000000000..df9eed5ea1 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> + +#include <arch/header.ld> + +/* + * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, + * so the bootblock loading address must be placed after that. After the + * handoff that area may be reclaimed for other uses, e.g. CBFS cache. + * TODO: Did this change on Tegra210? What's the new valid range? + */ + +SECTIONS +{ + SRAM_START(0x40000000) + PRERAM_CBMEM_CONSOLE(0x40000000, 8K) + PRERAM_CBFS_CACHE(0x40002000, 84K) + STACK(0x40017000, 16K) + BOOTBLOCK(0x4001B000, 26K) + ROMSTAGE(0x40022000, 120K) + SRAM_END(0x40040000) + + DRAM_START(0x80000000) + POSTRAM_CBFS_CACHE(0x80100000, 1M) + RAMSTAGE(0x80200000, 256K) +} diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld new file mode 100644 index 0000000000..7aa98e0e02 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> +#include <vendorcode/google/chromeos/memlayout.h> + +#include <arch/header.ld> + +/* + * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself, + * so the bootblock loading address must be placed after that. After the + * handoff that area may be reclaimed for other uses, e.g. CBFS cache. + * TODO: Did this change on Tegra210? What's the new valid range? + */ + +SECTIONS +{ + SRAM_START(0x40000000) + PRERAM_CBMEM_CONSOLE(0x40000000, 8K) + PRERAM_CBFS_CACHE(0x40002000, 72K) + VBOOT2_WORK(0x40014000, 16K) + STACK(0x40018000, 2K) + BOOTBLOCK(0x40019000, 24K) + VERSTAGE(0x4001F000, 56K) + ROMSTAGE(0x4002D000, 76K) + SRAM_END(0x40040000) + + DRAM_START(0x80000000) + POSTRAM_CBFS_CACHE(0x80100000, 1M) + RAMSTAGE(0x80200000, 256K) +} diff --git a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h new file mode 100644 index 0000000000..eb81719ace --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#ifndef _TEGRA_MIPI_PHY_H +#define _TEGRA_MIPI_PHY_H + +#include <stdlib.h> + +/* + * Macros for calculating the phy timings + */ +/* Period of one bit time in nano seconds */ +#define DSI_TBIT_Factorized(Freq) (((1000) * (1000))/(Freq)) +#define DSI_TBIT(Freq) (DSI_TBIT_Factorized(Freq)/(1000)) + +//#define NV_MAX(a,b) (((a) > (b)) ? (a) : (b)) + +/* Period of one byte time in nano seconds */ +#define DSI_TBYTE(Freq) ((DSI_TBIT_Factorized(Freq)) * (8)) +#define DSI_PHY_TIMING_DIV(X, Freq) ((X*1000) / (DSI_TBYTE(Freq))) + +/* + * As per Mipi spec (minimum): + * (3 + MAX(8 * DSI_TBIT, 60 + 4 * DSI_TBIT) / DSI_TBYTE) + */ +#define DSI_THSTRAIL_VAL(Freq) \ + (MAX(((8) * (DSI_TBIT(Freq))), ((60) + ((4) * (DSI_TBIT(Freq)))))) + +int mipi_dphy_set_timing(struct tegra_dsi *dsi); + +#endif diff --git a/src/soc/nvidia/tegra210/include/soc/mipi_display.h b/src/soc/nvidia/tegra210/include/soc/mipi_display.h new file mode 100644 index 0000000000..2e2e453432 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/mipi_display.h @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +/* + * Defines for Mobile Industry Processor Interface (MIPI(R)) + * Display Working Group standards: DSI, DCS, DBI, DPI + * + * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> + * Copyright (C) 2006 Nokia Corporation + * Author: Imre Deak <imre.deak@nokia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef MIPI_DISPLAY_H +#define MIPI_DISPLAY_H + +/* MIPI DSI Processor-to-Peripheral transaction types */ +enum { + MIPI_DSI_V_SYNC_START = 0x01, + MIPI_DSI_V_SYNC_END = 0x11, + MIPI_DSI_H_SYNC_START = 0x21, + MIPI_DSI_H_SYNC_END = 0x31, + + MIPI_DSI_COLOR_MODE_OFF = 0x02, + MIPI_DSI_COLOR_MODE_ON = 0x12, + MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, + MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, + + MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, + MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, + MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, + + MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, + MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, + MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, + + MIPI_DSI_DCS_SHORT_WRITE = 0x05, + MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, + + MIPI_DSI_DCS_READ = 0x06, + + MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, + + MIPI_DSI_END_OF_TRANSMISSION = 0x08, + + MIPI_DSI_NULL_PACKET = 0x09, + MIPI_DSI_BLANKING_PACKET = 0x19, + MIPI_DSI_GENERIC_LONG_WRITE = 0x29, + MIPI_DSI_DCS_LONG_WRITE = 0x39, + + MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, + + MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, + MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, + MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, + + MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, + MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, + MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, + MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, +}; + +/* MIPI DSI Peripheral-to-Processor transaction types */ +enum { + MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, + MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, + MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, + MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, + MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, + MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, +}; + +/* MIPI DCS commands */ +enum { + MIPI_DCS_NOP = 0x00, + MIPI_DCS_SOFT_RESET = 0x01, + MIPI_DCS_GET_DISPLAY_ID = 0x04, + MIPI_DCS_GET_RED_CHANNEL = 0x06, + MIPI_DCS_GET_GREEN_CHANNEL = 0x07, + MIPI_DCS_GET_BLUE_CHANNEL = 0x08, + MIPI_DCS_GET_DISPLAY_STATUS = 0x09, + MIPI_DCS_GET_POWER_MODE = 0x0A, + MIPI_DCS_GET_ADDRESS_MODE = 0x0B, + MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, + MIPI_DCS_GET_DISPLAY_MODE = 0x0D, + MIPI_DCS_GET_SIGNAL_MODE = 0x0E, + MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, + MIPI_DCS_ENTER_SLEEP_MODE = 0x10, + MIPI_DCS_EXIT_SLEEP_MODE = 0x11, + MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, + MIPI_DCS_ENTER_NORMAL_MODE = 0x13, + MIPI_DCS_EXIT_INVERT_MODE = 0x20, + MIPI_DCS_ENTER_INVERT_MODE = 0x21, + MIPI_DCS_SET_GAMMA_CURVE = 0x26, + MIPI_DCS_SET_DISPLAY_OFF = 0x28, + MIPI_DCS_SET_DISPLAY_ON = 0x29, + MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, + MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, + MIPI_DCS_WRITE_MEMORY_START = 0x2C, + MIPI_DCS_WRITE_LUT = 0x2D, + MIPI_DCS_READ_MEMORY_START = 0x2E, + MIPI_DCS_SET_PARTIAL_AREA = 0x30, + MIPI_DCS_SET_SCROLL_AREA = 0x33, + MIPI_DCS_SET_TEAR_OFF = 0x34, + MIPI_DCS_SET_TEAR_ON = 0x35, + MIPI_DCS_SET_ADDRESS_MODE = 0x36, + MIPI_DCS_SET_SCROLL_START = 0x37, + MIPI_DCS_EXIT_IDLE_MODE = 0x38, + MIPI_DCS_ENTER_IDLE_MODE = 0x39, + MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, + MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, + MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, + MIPI_DCS_SET_TEAR_SCANLINE = 0x44, + MIPI_DCS_GET_SCANLINE = 0x45, + MIPI_DCS_READ_DDB_START = 0xA1, + MIPI_DCS_READ_DDB_CONTINUE = 0xA8, +}; + +/* MIPI DCS pixel formats */ +#define MIPI_DCS_PIXEL_FMT_24BIT 7 +#define MIPI_DCS_PIXEL_FMT_18BIT 6 +#define MIPI_DCS_PIXEL_FMT_16BIT 5 +#define MIPI_DCS_PIXEL_FMT_12BIT 3 +#define MIPI_DCS_PIXEL_FMT_8BIT 2 +#define MIPI_DCS_PIXEL_FMT_3BIT 1 + +#endif diff --git a/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h b/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h new file mode 100644 index 0000000000..2d1e8b15d1 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/mipi_dsi.h @@ -0,0 +1,316 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +/* + * MIPI DSI Bus + * + * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd. + * Andrzej Hajda <a.hajda@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __MIPI_DSI_H__ +#define __MIPI_DSI_H__ + +struct mipi_dsi_host; +struct mipi_dsi_device; + +/* request ACK from peripheral */ +#define MIPI_DSI_MSG_REQ_ACK BIT(0) +/* use Low Power Mode to transmit message */ +#define MIPI_DSI_MSG_USE_LPM BIT(1) + +/** + * struct mipi_dsi_msg - read/write DSI buffer + * @channel: virtual channel id + * @type: payload data type + * @flags: flags controlling this message transmission + * @tx_len: length of @tx_buf + * @tx_buf: data to be written + * @rx_len: length of @rx_buf + * @rx_buf: data to be read, or NULL + */ +struct mipi_dsi_msg { + u8 channel; + u8 type; + u16 flags; + + size_t tx_len; + const void *tx_buf; + + size_t rx_len; + void *rx_buf; +}; + +/** + * struct mipi_dsi_host_ops - DSI bus operations + * @attach: attach DSI device to DSI host + * @detach: detach DSI device from DSI host + * @transfer: transmit a DSI packet + * + * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg + * structures. This structure contains information about the type of packet + * being transmitted as well as the transmit and receive buffers. When an + * error is encountered during transmission, this function will return a + * negative error code. On success it shall return the number of bytes + * transmitted for write packets or the number of bytes received for read + * packets. + * + * Note that typically DSI packet transmission is atomic, so the .transfer() + * function will seldomly return anything other than the number of bytes + * contained in the transmit buffer on success. + */ +struct mipi_dsi_host_ops { + int (*attach)(struct mipi_dsi_host *host, + struct mipi_dsi_device *dsi); + int (*detach)(struct mipi_dsi_host *host, + struct mipi_dsi_device *dsi); + ssize_t (*transfer)(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg); +}; + +/** + * struct mipi_dsi_host - DSI host device + * @dev: driver model device node for this DSI host + * @ops: DSI host operations + */ +struct mipi_dsi_host { + //struct device *dev; + void *dev; + const struct mipi_dsi_host_ops *ops; +}; + +int mipi_dsi_host_register(struct mipi_dsi_host *host); + +/* DSI mode flags */ + +/* video mode */ +#define MIPI_DSI_MODE_VIDEO BIT(0) +/* video burst mode */ +#define MIPI_DSI_MODE_VIDEO_BURST BIT(1) +/* video pulse mode */ +#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2) +/* enable auto vertical count mode */ +#define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3) +/* enable hsync-end packets in vsync-pulse and v-porch area */ +#define MIPI_DSI_MODE_VIDEO_HSE BIT(4) +/* disable hfront-porch area */ +#define MIPI_DSI_MODE_VIDEO_HFP BIT(5) +/* disable hback-porch area */ +#define MIPI_DSI_MODE_VIDEO_HBP BIT(6) +/* disable hsync-active area */ +#define MIPI_DSI_MODE_VIDEO_HSA BIT(7) +/* flush display FIFO on vsync pulse */ +#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) +/* disable EoT packets in HS mode */ +#define MIPI_DSI_MODE_EOT_PACKET BIT(9) +/* device supports non-continuous clock behavior (DSI spec 5.6.1) */ +#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) + +enum mipi_dsi_pixel_format { + MIPI_DSI_FMT_RGB888, + MIPI_DSI_FMT_RGB666, + MIPI_DSI_FMT_RGB666_PACKED, + MIPI_DSI_FMT_RGB565, +}; + +struct mipi_dsi_master_ops { + int (*enslave)(struct mipi_dsi_device *master, + struct mipi_dsi_device *slave); + int (*liberate)(struct mipi_dsi_device *master, + struct mipi_dsi_device *slave); +}; + +/** + * struct mipi_dsi_device - DSI peripheral device + * @host: DSI host for this peripheral + * @dev: driver model device node for this peripheral + * @channel: virtual channel assigned to the peripheral + * @format: pixel format for video mode + * @lanes: number of active data lanes + * @mode_flags: DSI operation mode related flags + * @ops: callbacks for master/slave setup + * @master: master interface for dual-channel peripherals + * @slave: slave interface for dual-channel peripherals + * + * For dual-channel interfaces, the master interface can be identified by the + * fact that it's .slave field is set to non-NULL. The slave interface will + * have the .master field set to non-NULL. + */ +struct mipi_dsi_device { + struct mipi_dsi_host *host; + + unsigned int channel; + unsigned int lanes; + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; + + const struct mipi_dsi_master_ops *ops; + struct mipi_dsi_device *master; + struct mipi_dsi_device *slave; +}; + +int mipi_dsi_attach(struct mipi_dsi_device *dsi); +int mipi_dsi_detach(struct mipi_dsi_device *dsi); +int mipi_dsi_enslave(struct mipi_dsi_device *master, + struct mipi_dsi_device *slave); +int mipi_dsi_liberate(struct mipi_dsi_device *master, + struct mipi_dsi_device *slave); + +/** + * enum mipi_dsi_dcs_tear_mode - Tearing Effect Output Line mode + * @MIPI_DSI_DCS_TEAR_MODE_VBLANK: the TE output line consists of V-Blanking + * information only + * @MIPI_DSI_DCS_TEAR_MODE_VHBLANK : the TE output line consists of both + * V-Blanking and H-Blanking information + */ +enum mipi_dsi_dcs_tear_mode { + MIPI_DSI_DCS_TEAR_MODE_VBLANK, + MIPI_DSI_DCS_TEAR_MODE_VHBLANK, +}; + +#define MIPI_DSI_DCS_POWER_MODE_DISPLAY (1 << 2) +#define MIPI_DSI_DCS_POWER_MODE_NORMAL (1 << 3) +#define MIPI_DSI_DCS_POWER_MODE_SLEEP (1 << 4) +#define MIPI_DSI_DCS_POWER_MODE_PARTIAL (1 << 5) +#define MIPI_DSI_DCS_POWER_MODE_IDLE (1 << 6) + +ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd, + const void *data, size_t len); +int mipi_dsi_dcs_exit_sleep_mode(struct mipi_dsi_device *dsi); +int mipi_dsi_dcs_set_display_on(struct mipi_dsi_device *dsi); +int mipi_dsi_dcs_set_column_address(struct mipi_dsi_device *dsi, u16 start, + u16 end); +int mipi_dsi_dcs_set_page_address(struct mipi_dsi_device *dsi, u16 start, + u16 end); +int mipi_dsi_dcs_set_address_mode(struct mipi_dsi_device *dsi, + bool reverse_page_address, + bool reverse_col_address, + bool reverse_page_col_address, + bool refresh_from_bottom, + bool reverse_rgb, + bool latch_right_to_left, + bool flip_horizontal, + bool flip_vertical); +int mipi_dsi_dcs_set_tear_on(struct mipi_dsi_device *dsi, + enum mipi_dsi_dcs_tear_mode mode); +int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format); + +#define MIPI_CAL_CTRL 0x00 +#define MIPI_CAL_CTRL_NOISE_FILTER(x) (((x) & 0xf) << 26) +#define MIPI_CAL_CTRL_PRESCALE(x) (((x) & 0x3) << 24) +#define MIPI_CAL_CTRL_CLKEN_OVR (1 << 4) +#define MIPI_CAL_CTRL_START (1 << 0) + +#define MIPI_CAL_AUTOCAL_CTRL 0x01 + +#define MIPI_CAL_STATUS 0x02 +#define MIPI_CAL_STATUS_DONE (1 << 16) +#define MIPI_CAL_STATUS_ACTIVE (1 << 0) + +#define MIPI_CAL_CONFIG_CSIA 0x05 +#define MIPI_CAL_CONFIG_CSIB 0x06 +#define MIPI_CAL_CONFIG_CSIC 0x07 +#define MIPI_CAL_CONFIG_CSID 0x08 +#define MIPI_CAL_CONFIG_CSIE 0x09 +#define MIPI_CAL_CONFIG_CSIF 0x0a +#define MIPI_CAL_CONFIG_DSIA 0x0e +#define MIPI_CAL_CONFIG_DSIB 0x0f +#define MIPI_CAL_CONFIG_DSIC 0x10 +#define MIPI_CAL_CONFIG_DSID 0x11 + +#define MIPI_CAL_CONFIG_DSIA_CLK 0x19 +#define MIPI_CAL_CONFIG_DSIB_CLK 0x1a +#define MIPI_CAL_CONFIG_CSIAB_CLK 0x1b +#define MIPI_CAL_CONFIG_DSIC_CLK 0x1c +#define MIPI_CAL_CONFIG_CSICD_CLK 0x1c +#define MIPI_CAL_CONFIG_DSID_CLK 0x1d +#define MIPI_CAL_CONFIG_CSIE_CLK 0x1d + +/* for data and clock lanes */ +#define MIPI_CAL_CONFIG_SELECT (1 << 21) + +/* for data lanes */ +#define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16) +#define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0) + +/* for clock lanes */ +#define MIPI_CAL_CONFIG_HSCLKPDOSD(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_CONFIG_HSCLKPUOSD(x) (((x) & 0x1f) << 0) + +#define MIPI_CAL_BIAS_PAD_CFG0 0x16 +#define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1) +#define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0) + +#define MIPI_CAL_BIAS_PAD_CFG1 0x17 +#define MIPI_CAL_BIAS_PAD_DRV_DN_REF(x) (((x) & 0x7) << 16) +#define MIPI_CAL_BIAS_PAD_DRV_UP_REF(x) (((x) & 0x7) << 8) + +#define MIPI_CAL_BIAS_PAD_CFG2 0x18 +#define MIPI_CAL_BIAS_PAD_VCLAMP(x) (((x) & 0x7) << 16) +#define MIPI_CAL_BIAS_PAD_VAUXP(x) (((x) & 0x7) << 4) +#define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1) + +struct tegra_mipi_pad { + unsigned long data; + unsigned long clk; +}; + +struct tegra_mipi_soc { + int has_clk_lane; + const struct tegra_mipi_pad *pads; + unsigned int num_pads; + + int clock_enable_override; + int needs_vclamp_ref; + + /* bias pad configuration settings */ + u8 pad_drive_down_ref; + u8 pad_drive_up_ref; + + u8 pad_vclamp_level; + u8 pad_vauxp_level; + + /* calibration settings for data lanes */ + u8 hspdos; + u8 hspuos; + u8 termos; + + /* calibration settings for clock lanes */ + u8 hsclkpdos; + u8 hsclkpuos; +}; + +struct tegra_mipi { + const struct tegra_mipi_soc *soc; + void *regs; +}; + +struct tegra_mipi_device { + struct tegra_mipi *mipi; + unsigned long pads; +}; + +struct tegra_mipi_device *tegra_mipi_request(struct tegra_mipi_device *device, + int device_index); +int tegra_mipi_calibrate(struct tegra_mipi_device *device); +#endif /* __MIPI_DSI_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/mmu_operations.h b/src/soc/nvidia/tegra210/include/soc/mmu_operations.h new file mode 100644 index 0000000000..6a81e7c321 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/mmu_operations.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_MMU_OPERATIONS_H__ +#define __SOC_NVIDIA_TEGRA210_MMU_OPERATIONS_H__ + +void tegra210_mmu_init(void); + +/* Default ttb size of 4MiB */ +#define TTB_SIZE 0x4 + +#endif //__SOC_NVIDIA_TEGRA210_MMU_OPERATIONS_H__ diff --git a/src/soc/nvidia/tegra210/include/soc/mtc.h b/src/soc/nvidia/tegra210/include/soc/mtc.h new file mode 100644 index 0000000000..c94d79b988 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/mtc.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_MTC_H__ +#define __SOC_NVIDIA_TEGRA210_MTC_H__ + +#include <boot/coreboot_tables.h> + +#if CONFIG_HAVE_MTC + +int tegra210_run_mtc(void); +void soc_add_mtc(struct lb_header *header); + +#else + +static inline int tegra210_run_mtc(void) { return -1; } +static inline void soc_add_mtc(struct lb_header *header) {} + +#endif /* CONFIG_HAVE_MTC */ + +#endif /* __SOC_NVIDIA_TEGRA210_MTC_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/padconfig.h b/src/soc/nvidia/tegra210/include/soc/padconfig.h new file mode 100644 index 0000000000..01cd72a4a9 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/padconfig.h @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_PAD_CFG_H +#define __SOC_NVIDIA_TEGRA210_PAD_CFG_H + +#include <stdint.h> +#include <soc/pinmux.h> + +struct pad_config { + uint16_t pinmux_flags; /* PU/PU, OD, INPUT, SFIO, etc */ + uint8_t gpio_index; /* bank, port, index */ + uint16_t pinmux_index:9; + uint16_t unused:1; + uint16_t sfio:1; + uint16_t gpio_out0:1; + uint16_t gpio_out1:1; + uint16_t pad_has_gpio:1; + uint16_t por_pullup:1; +}; + +#define PAD_CFG_GPIO_INPUT(ball_, pinmux_flgs_) \ + { \ + .pinmux_flags = pinmux_flgs_ | PINMUX_INPUT_ENABLE, \ + .gpio_index = PAD_TO_GPIO_##ball_, \ + .pinmux_index = PINMUX_##ball_##_INDEX, \ + .sfio = 0, \ + .pad_has_gpio = PAD_HAS_GPIO_##ball_, \ + } + +#define PAD_CFG_GPIO_OUT0(ball_, pinmux_flgs_) \ + { \ + .pinmux_flags = pinmux_flgs_, \ + .gpio_index = PAD_TO_GPIO_##ball_, \ + .pinmux_index = PINMUX_##ball_##_INDEX, \ + .sfio = 0, \ + .gpio_out0 = 1, \ + .pad_has_gpio = PAD_HAS_GPIO_##ball_, \ + } + +#define PAD_CFG_GPIO_OUT1(ball_, pinmux_flgs_) \ + { \ + .pinmux_flags = pinmux_flgs_, \ + .gpio_index = PAD_TO_GPIO_##ball_, \ + .pinmux_index = PINMUX_##ball_##_INDEX, \ + .sfio = 0, \ + .gpio_out1 = 1, \ + .pad_has_gpio = PAD_HAS_GPIO_##ball_, \ + } + +#define PAD_CFG_SFIO(ball_, pinmux_flgs_, sfio_) \ + { \ + .pinmux_flags = pinmux_flgs_ | \ + PINMUX_##ball_##_FUNC_##sfio_, \ + .gpio_index = PAD_TO_GPIO_##ball_, \ + .pinmux_index = PINMUX_##ball_##_INDEX, \ + .sfio = 1, \ + .pad_has_gpio = PAD_HAS_GPIO_##ball_, \ + } + +#define PAD_CFG_UNUSED(ball_) \ + { \ + .gpio_index = PAD_TO_GPIO_##ball_, \ + .pinmux_index = PINMUX_##ball_##_INDEX, \ + .unused = 1, \ + .pad_has_gpio = PAD_HAS_GPIO_##ball_, \ + } +/* + * Configure the pads associated with entry according to the configuration. + */ +void soc_configure_pads(const struct pad_config * const entries, size_t num); +/* I2C6 requires special init as its pad lives int the SOR/DPAUX block */ +void soc_configure_i2c6pad(void); +void soc_configure_host1x(void); +/* APE (Audio Processing Engine) requires special init */ +void soc_configure_ape(void); + +#endif /* __SOC_NVIDIA_TEGRA210_PAD_CFG_H */ diff --git a/src/soc/nvidia/tegra210/include/soc/pinmux.h b/src/soc/nvidia/tegra210/include/soc/pinmux.h new file mode 100644 index 0000000000..ab59fbf076 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/pinmux.h @@ -0,0 +1,285 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_PINMUX_H__ +#define __SOC_NVIDIA_TEGRA210_PINMUX_H__ + +#include <stdint.h> +#include <soc/nvidia/tegra/gpio.h> +#include <soc/nvidia/tegra/pinmux.h> + +enum { + PINMUX_FUNC_MASK = 3 << 0, + + PINMUX_PULL_MASK = 3 << 2, + PINMUX_PULL_NONE = 0 << 2, + PINMUX_PULL_DOWN = 1 << 2, + PINMUX_PULL_UP = 2 << 2, + + PINMUX_TRISTATE = 1 << 4, + PINMUX_PARKED = 1 << 5, + PINMUX_INPUT_ENABLE = 1 << 6, + PINMUX_LOCK = 1 << 7, + PINMUX_LPDR = 1 << 8, + PINMUX_HSM = 1 << 9, + PINMUX_IO_HV = 1 << 10, + PINMUX_OPEN_DRAIN = 1 << 11, + PINMUX_SCHMT = 1 << 12, +}; + +/* GPIO index constants. */ + +#define GPIO_PORT_CONSTANTS(port) \ + GPIO_##port##0_INDEX, GPIO_##port##1_INDEX, GPIO_##port##2_INDEX, \ + GPIO_##port##3_INDEX, GPIO_##port##4_INDEX, GPIO_##port##5_INDEX, \ + GPIO_##port##6_INDEX, GPIO_##port##7_INDEX + +enum { + GPIO_PORT_CONSTANTS(A), + GPIO_PORT_CONSTANTS(B), + GPIO_PORT_CONSTANTS(C), + GPIO_PORT_CONSTANTS(D), + GPIO_PORT_CONSTANTS(E), + GPIO_PORT_CONSTANTS(F), + GPIO_PORT_CONSTANTS(G), + GPIO_PORT_CONSTANTS(H), + GPIO_PORT_CONSTANTS(I), + GPIO_PORT_CONSTANTS(J), + GPIO_PORT_CONSTANTS(K), + GPIO_PORT_CONSTANTS(L), + GPIO_PORT_CONSTANTS(M), + GPIO_PORT_CONSTANTS(N), + GPIO_PORT_CONSTANTS(O), + GPIO_PORT_CONSTANTS(P), + GPIO_PORT_CONSTANTS(Q), + GPIO_PORT_CONSTANTS(R), + GPIO_PORT_CONSTANTS(S), + GPIO_PORT_CONSTANTS(T), + GPIO_PORT_CONSTANTS(U), + GPIO_PORT_CONSTANTS(V), + GPIO_PORT_CONSTANTS(W), + GPIO_PORT_CONSTANTS(X), + GPIO_PORT_CONSTANTS(Y), + GPIO_PORT_CONSTANTS(Z), + GPIO_PORT_CONSTANTS(AA), + GPIO_PORT_CONSTANTS(BB), + GPIO_PORT_CONSTANTS(CC), + GPIO_PORT_CONSTANTS(DD), + GPIO_PORT_CONSTANTS(EE), + GPIO_PORT_CONSTANTS(FF), + GPIO_NONE_INDEX = 0, +}; + +#define PINMUX_CONSTANTS_GPIO(name, gpio) \ + PINMUX_GPIO_##gpio = PINMUX_##name##_INDEX + +#define PINMUX_CONSTANTS(index, name, por_pu, gpio, has_gpio, \ + func0, func1, func2, func3) \ + PINMUX_##name##_INDEX = index, \ + PINMUX_##name##_FUNC_##func0 = 0, \ + PINMUX_##name##_FUNC_##func1 = 1, \ + PINMUX_##name##_FUNC_##func2 = 2, \ + PINMUX_##name##_FUNC_##func3 = 3, \ + PAD_TO_GPIO_##name = GPIO_##gpio##_INDEX, \ + PAD_HAS_GPIO_##name = has_gpio, \ + PAD_POR_PU_##name = por_pu + +#define PAD_GPIO(index, name, por_pu, gpio, func0, func1, func2, func3) \ + PINMUX_CONSTANTS(index, name, por_pu, gpio, 1, \ + func0, func1, func2, func3), \ + PINMUX_CONSTANTS_GPIO(name, gpio) + +#define PAD_NO_GPIO(index, name, por_pu, func0, func1, func2, func3) \ + PINMUX_CONSTANTS(index, name, por_pu, NONE, 0, \ + func0, func1, func2, func3) + +enum { + /* Power-on-reset pull states. */ + POR_PU = 2, + POR_PD = 1, + POR_NP = 0, + + PAD_GPIO(0, SDMMC1_CLK, POR_PD, M0, SDMMC1, RES1, RES2, RES3), + PAD_GPIO(1, SDMMC1_CMD, POR_PU, M1, SDMMC1, RES1, RES2, RES3), + PAD_GPIO(2, SDMMC1_DAT3, POR_PU, M2, SDMMC1, RES1, RES2, RES3), + PAD_GPIO(3, SDMMC1_DAT2, POR_PU, M3, SDMMC1, RES1, RES2, RES3), + PAD_GPIO(4, SDMMC1_DAT1, POR_PU, M4, SDMMC1, RES1, RES2, RES3), + PAD_GPIO(5, SDMMC1_DAT0, POR_PU, M5, SDMMC1, RES1, RES2, RES3), + PAD_GPIO(6, SDMMC3_CLK, POR_PD, P0, SDMMC3, RES1, RES2, RES3), + PAD_GPIO(7, SDMMC3_CMD, POR_PU, P1, SDMMC3, RES1, RES2, RES3), + PAD_GPIO(8, SDMMC3_DAT0, POR_PU, P2, SDMMC3, RES1, RES2, RES3), + PAD_GPIO(9, SDMMC3_DAT1, POR_PU, P3, SDMMC3, RES1, RES2, RES3), + PAD_GPIO(10, SDMMC3_DAT2, POR_PU, P4, SDMMC3, RES1, RES2, RES3), + PAD_GPIO(11, SDMMC3_DAT3, POR_PU, P5, SDMMC3, RES1, RES2, RES3), + /* GPIO12 - unused */ + /* GPIO13 - unused */ + PAD_GPIO(14, PEX_L0_RST_N, POR_NP, A0, PE0, RES1, RES2, RES3), + PAD_GPIO(15, PEX_L0_CLKREQ_N, POR_NP, A1, PE0, RES1, RES2, RES3), + PAD_GPIO(16, PEX_WAKE_N, POR_NP, A2, PE, RES1, RES2, RES3), + PAD_GPIO(17, PEX_L1_RST_N, POR_NP, A3, PE1, RES1, RES2, RES3), + PAD_GPIO(18, PEX_L1_CLKREQ_N, POR_NP, A4, PE1, RES1, RES2, RES3), + PAD_GPIO(19, SATA_LED_ACTIVE, POR_NP, A5, SATA, RES1, RES2, RES3), + PAD_GPIO(20, SPI1_MOSI, POR_PD, C0, SPI1, RES1, RES2, RES3), + PAD_GPIO(21, SPI1_MISO, POR_PD, C1, SPI1, RES1, RES2, RES3), + PAD_GPIO(22, SPI1_SCK, POR_PD, C2, SPI1, RES1, RES2, RES3), + PAD_GPIO(23, SPI1_CS0, POR_PU, C3, SPI1, RES1, RES2, RES3), + PAD_GPIO(24, SPI1_CS1, POR_PU, C4, SPI1, RES1, RES2, RES3), + PAD_GPIO(25, SPI2_MOSI, POR_PD, B4, SPI2, DTV, RES2, RES3), + PAD_GPIO(26, SPI2_MISO, POR_PD, B5, SPI2, DTV, RES2, RES3), + PAD_GPIO(27, SPI2_SCK, POR_PD, B6, SPI2, DTV, RES2, RES3), + PAD_GPIO(28, SPI2_CS0, POR_PU, B7, SPI2, DTV, RES2, RES3), + PAD_GPIO(29, SPI2_CS1, POR_PU, DD0, SPI2, RES1, RES2, RES3), + PAD_GPIO(30, SPI4_MOSI, POR_PD, C7, SPI4, RES1, RES2, RES3), + PAD_GPIO(31, SPI4_MISO, POR_PD, D0, SPI4, RES1, RES2, RES3), + PAD_GPIO(32, SPI4_SCK, POR_PD, C5, SPI4, RES1, RES2, RES3), + PAD_GPIO(33, SPI4_CS0, POR_PU, C6, SPI4, RES1, RES2, RES3), + PAD_GPIO(34, QSPI_SCK, POR_PU, EE0, QSPI, RES1, RES2, RES3), + PAD_GPIO(35, QSPI_CS_N, POR_PU, EE1, QSPI, RES1, RES2, RES3), + PAD_GPIO(36, QSPI_IO0, POR_PU, EE2, QSPI, RES1, RES2, RES3), + PAD_GPIO(37, QSPI_IO1, POR_PU, EE3, QSPI, RES1, RES2, RES3), + PAD_GPIO(38, QSPI_IO2, POR_PU, EE4, QSPI, RES1, RES2, RES3), + PAD_GPIO(39, QSPI_IO3, POR_PU, EE5, QSPI, RES1, RES2, RES3), + /* GPIO40 - unused */ + PAD_GPIO(41, DMIC1_CLK, POR_PD, E0, DMIC1, I2S3, RES2, RES3), + PAD_GPIO(42, DMIC1_DAT, POR_PD, E1, DMIC1, I2S3, RES2, RES3), + PAD_GPIO(43, DMIC2_CLK, POR_PD, E2, DMIC2, I2S3, RES2, RES3), + PAD_GPIO(44, DMIC2_DAT, POR_PD, E3, DMIC2, I2S3, RES2, RES3), + PAD_GPIO(45, DMIC3_CLK, POR_PD, E4, DMIC3, I2S5A, RES2, RES3), + PAD_GPIO(46, DMIC3_DAT, POR_PD, E5, DMIC3, I2S5A, RES2, RES3), + PAD_GPIO(47, GEN1_I2C_SDA, POR_NP, J0, I2C1, RES1, RES2, RES3), + PAD_GPIO(48, GEN1_I2C_SCL, POR_NP, J1, I2C1, RES1, RES2, RES3), + PAD_GPIO(49, GEN2_I2C_SCL, POR_NP, J2, I2C2, RES1, RES2, RES3), + PAD_GPIO(50, GEN2_I2C_SDA, POR_NP, J3, I2C2, RES1, RES2, RES3), + PAD_GPIO(51, GEN3_I2C_SCL, POR_NP, F0, I2C3, RES1, RES2, RES3), + PAD_GPIO(52, GEN3_I2C_SDA, POR_NP, F1, I2C3, RES1, RES2, RES3), + PAD_GPIO(53, CAM_I2C_SCL, POR_NP, S2, I2C3, I2CVI, RES2, RES3), + PAD_GPIO(54, CAM_I2C_SDA, POR_NP, S3, I2C3, I2CVI, RES2, RES3), + PAD_GPIO(55, PWR_I2C_SCL, POR_NP, Y3, I2CPMU, RES1, RES2, RES3), + PAD_GPIO(56, PWR_I2C_SDA, POR_NP, Y4, I2CPMU, RES1, RES2, RES3), + PAD_GPIO(57, UART1_TX, POR_PD, U0, UARTA, RES1, RES2, RES3), + PAD_GPIO(58, UART1_RX, POR_PD, U1, UARTA, RES1, RES2, RES3), + PAD_GPIO(59, UART1_RTS, POR_PD, U2, UARTA, RES1, RES2, RES3), + PAD_GPIO(60, UART1_CTS, POR_PD, U3, UARTA, RES1, RES2, RES3), + PAD_GPIO(61, UART2_TX, POR_PD, G0, UARTB, I2S4A, SPDIF, UART), + PAD_GPIO(62, UART2_RX, POR_PD, G1, UARTB, I2S4A, SPDIF, UART), + PAD_GPIO(63, UART2_RTS, POR_PD, G2, UARTB, I2S4A, RES2, UART), + PAD_GPIO(64, UART2_CTS, POR_PD, G3, UARTB, I2S4A, RES2, UART), + PAD_GPIO(65, UART3_TX, POR_PD, D1, UARTC, SPI4, RES2, RES3), + PAD_GPIO(66, UART3_RX, POR_PD, D2, UARTC, SPI4, RES2, RES3), + PAD_GPIO(67, UART3_RTS, POR_PD, D3, UARTC, SPI4, RES2, RES3), + PAD_GPIO(68, UART3_CTS, POR_PD, D4, UARTC, SPI4, RES2, RES3), + PAD_GPIO(69, UART4_TX, POR_PD, I4, UARTD, UART, RES2, RES3), + PAD_GPIO(70, UART4_RX, POR_PD, I5, UARTD, UART, RES2, RES3), + PAD_GPIO(71, UART4_RTS, POR_PD, I6, UARTD, UART, RES2, RES3), + PAD_GPIO(72, UART4_CTS, POR_PD, I7, UARTD, UART, RES2, RES3), + PAD_GPIO(73, DAP1_FS, POR_PD, B0, I2S1, RES1, RES2, RES3), + PAD_GPIO(74, DAP1_DIN, POR_PD, B1, I2S1, RES1, RES2, RES3), + PAD_GPIO(75, DAP1_DOUT, POR_PD, B2, I2S1, RES1, RES2, RES3), + PAD_GPIO(76, DAP1_SCLK, POR_PD, B3, I2S1, RES1, RES2, RES3), + PAD_GPIO(77, DAP2_FS, POR_PD, AA0, I2S2, RES1, RES2, RES3), + PAD_GPIO(78, DAP2_DIN, POR_PD, AA1, I2S2, RES1, RES2, RES3), + PAD_GPIO(79, DAP2_DOUT, POR_PD, AA2, I2S2, RES1, RES2, RES3), + PAD_GPIO(80, DAP2_SCLK, POR_PD, AA3, I2S2, RES1, RES2, RES3), + PAD_GPIO(81, DAP4_FS, POR_PD, J4, I2S4B, RES1, RES2, RES3), + PAD_GPIO(82, DAP4_DIN, POR_PD, J5, I2S4B, RES1, RES2, RES3), + PAD_GPIO(83, DAP4_DOUT, POR_PD, J6, I2S4B, RES1, RES2, RES3), + PAD_GPIO(84, DAP4_SCLK, POR_PD, J7, I2S4B, RES1, RES2, RES3), + PAD_GPIO(85, CAM1_MCLK, POR_PD, S0, EXTPERIPH3, RES1, RES2, RES3), + PAD_GPIO(86, CAM2_MCLK, POR_PD, S1, EXTPERIPH3, RES1, RES2, RES3), + PAD_NO_GPIO(87, JTAG_RTCK, POR_PU, JTAG, RES1, RES2, RES3), + PAD_NO_GPIO(88, CLK_32K_IN, POR_NP, CLK_32K_IN, RES1, RES2, RES3), + PAD_GPIO(89, CLK_32K_OUT, POR_PD, Y5, SOC, BLINK, RES2, RES3), + PAD_NO_GPIO(90, BATT_BCL, POR_NP, BCL, RES1, RES2, RES3), + PAD_NO_GPIO(91, CLK_REQ, POR_NP, CLK_REQ, RES1, RES2, RES3), + PAD_NO_GPIO(92, CPU_PWR_REQ, POR_NP, CPU, RES1, RES2, RES3), + PAD_NO_GPIO(93, PWR_INT_N, POR_NP, PMI, RES1, RES2, RES3), + PAD_NO_GPIO(94, SHUTDOWN, POR_NP, SHUTDOWN, RES1, RES2, RES3), + PAD_NO_GPIO(95, CORE_PWR_REQ, POR_NP, PWRON, RES1, RES2, RES3), + PAD_GPIO(96, AUD_MCLK, POR_PD, BB0, AUD, RES1, RES2, RES3), + PAD_GPIO(97, DVFS_PWM, POR_PD, BB1, RES0, CLDVFS, SPI3, RES3), + PAD_GPIO(98, DVFS_CLK, POR_PU, BB2, RES0, CLDVFS, SPI3, RES3), + PAD_GPIO(99, GPIO_X1_AUD, POR_PD, BB3, RES0, RES1, SPI3, RES3), + PAD_GPIO(100, GPIO_X3_AUD, POR_PU, BB4, RES0, RES1, SPI3, RES3), + PAD_NO_GPIO(101, GPIO_PCC7, POR_NP, RES0, RES1, RES2, RES3), + PAD_GPIO(102, HDMI_CEC, POR_NP, CC0, CEC, RES1, RES2, RES3), + PAD_GPIO(103, HDMI_INT_DP_HPD, POR_PD, CC1, DP, RES1, RES2, RES3), + PAD_GPIO(104, SPDIF_OUT, POR_PU, CC2, SPDIF, RES1, RES2, I2C3), + PAD_GPIO(105, SPDIF_IN, POR_PD, CC3, SPDIF, RES1, RES2, I2C3), + PAD_GPIO(106, USB_VBUS_EN0, POR_NP, CC4, USB, RES1, RES2, RES3), + PAD_GPIO(107, USB_VBUS_EN1, POR_NP, CC5, USB, RES1, RES2, RES3), + PAD_GPIO(108, DP_HPD0, POR_PD, CC6, DP, RES1, RES2, RES3), + PAD_GPIO(109, WIFI_EN, POR_PD, H0, RES0, RES1, RES2, RES3), + PAD_GPIO(110, WIFI_RST, POR_PD, H1, RES0, RES1, RES2, RES3), + PAD_GPIO(111, WIFI_WAKE_AP, POR_PD, H2, RES0, RES1, RES2, RES3), + PAD_GPIO(112, AP_WAKE_BT, POR_PD, H3, RES0, UARTB, SPDIF, RES3), + PAD_GPIO(113, BT_RST, POR_PD, H4, RES0, UARTB, SPDIF, RES3), + PAD_GPIO(114, BT_WAKE_AP, POR_PD, H5, RES0, RES1, RES2, RES3), + PAD_GPIO(115, AP_WAKE_NFC, POR_PD, H7, RES0, RES1, RES2, RES3), + PAD_GPIO(116, NFC_EN, POR_PD, I0, RES0, RES1, RES2, RES3), + PAD_GPIO(117, NFC_INT, POR_PD, I1, RES0, RES1, RES2, RES3), + PAD_GPIO(118, GPS_EN, POR_PD, I2, RES0, RES1, RES2, RES3), + PAD_GPIO(119, GPS_RST, POR_PD, I3, RES0, RES1, RES2, RES3), + PAD_GPIO(120, CAM_RST, POR_PD, S4, VGP1, RES1, RES2, RES3), + PAD_GPIO(121, CAM_AF_EN, POR_PD, S5, VIMCLK, VGP2, RES2, RES3), + PAD_GPIO(122, CAM_FLASH_EN, POR_PD, S6, VIMCLK, VGP3, RES2, RES3), + PAD_GPIO(123, CAM1_PWDN, POR_PD, S7, VGP4, RES1, RES2, RES3), + PAD_GPIO(124, CAM2_PWDN, POR_PD, T0, VGP5, RES1, RES2, RES3), + PAD_GPIO(125, CAM1_STROBE, POR_PD, T1, VGP6, RES1, RES2, RES3), + PAD_GPIO(126, LCD_TE, POR_PD, Y2, DISPLAYA, RES1, RES2, RES3), + PAD_GPIO(127, LCD_BL_PWM, POR_PD, V0, DISPLAYA, PWM0, SOR0, RES3), + PAD_GPIO(128, LCD_BL_EN, POR_PD, V1, RES0, RES1, RES2, RES3), + PAD_GPIO(129, LCD_RST, POR_PD, V2, RES0, RES1, RES2, RES3), + PAD_GPIO(130, LCD_GPIO1, POR_PD, V3, DISPLAYB, RES1, RES2, RES3), + PAD_GPIO(131, LCD_GPIO2, POR_PD, V4, DISPLAYB, PWM1, RES2, SOR1), + PAD_GPIO(132, AP_READY, POR_PD, V5, RES0, RES1, RES2, RES3), + PAD_GPIO(133, TOUCH_RST, POR_PD, V6, RES0, RES1, RES2, RES3), + PAD_GPIO(134, TOUCH_CLK, POR_PD, V7, TOUCH, RES1, RES2, RES3), + PAD_GPIO(135, MODEM_WAKE_AP, POR_PD, X0, RES0, RES1, RES2, RES3), + PAD_GPIO(136, TOUCH_INT, POR_PD, X1, RES0, RES1, RES2, RES3), + PAD_GPIO(137, MOTION_INT, POR_PD, X2, RES0, RES1, RES2, RES3), + PAD_GPIO(138, ALS_PROX_INT, POR_PD, X3, RES0, RES1, RES2, RES3), + PAD_GPIO(139, TEMP_ALERT, POR_PD, X4, RES0, RES1, RES2, RES3), + PAD_GPIO(140, BUTTON_POWER_ON, POR_PU, X5, RES0, RES1, RES2, RES3), + PAD_GPIO(141, BUTTON_VOL_UP, POR_PU, X6, RES0, RES1, RES2, RES3), + PAD_GPIO(142, BUTTON_VOL_DOWN, POR_PU, X7, RES0, RES1, RES2, RES3), + PAD_GPIO(143, BUTTON_SLIDE_SW, POR_PU, Y0, RES0, RES1, RES2, RES3), + PAD_GPIO(144, BUTTON_HOME, POR_PU, Y1, RES0, RES1, RES2, RES3), + PAD_NO_GPIO(145, GPIO_PA6, POR_NP, SATA, RES1, RES2, RES3), + PAD_NO_GPIO(146, GPIO_PE6, POR_PD, RES0, I2S5A, PWM2, RES3), + PAD_NO_GPIO(147, GPIO_PE7, POR_PD, RES0, I2S5A, PWM3, RES3), + PAD_NO_GPIO(148, GPIO_PH6, POR_PD, RES0, RES1, RES2, RES3), + PAD_GPIO(149, GPIO_PK0, POR_PD, K0, IQC0, I2S5B, RES2, RES3), + PAD_GPIO(150, GPIO_PK1, POR_PD, K1, IQC0, I2S5B, RES2, RES3), + PAD_GPIO(151, GPIO_PK2, POR_PD, K2, IQC0, I2S5B, RES2, RES3), + PAD_NO_GPIO(152, GPIO_PK3, POR_PD, IQC0, I2S5B, RES2, RES3), + PAD_NO_GPIO(153, GPIO_PK4, POR_PD, IQC1, RES1, RES2, RES3), + PAD_NO_GPIO(154, GPIO_PK5, POR_PD, IQC1, RES1, RES2, RES3), + PAD_NO_GPIO(155, GPIO_PK6, POR_PD, IQC1, RES1, RES2, RES3), + PAD_NO_GPIO(156, GPIO_PK7, POR_PD, IQC1, RES1, RES2, RES3), + PAD_NO_GPIO(157, GPIO_PL0, POR_PD, RES0, RES1, RES2, RES3), + PAD_NO_GPIO(158, GPIO_PL1, POR_PD, SOC, RES1, RES2, RES3), + PAD_NO_GPIO(159, GPIO_PZ0, POR_PD, VIMCLK2, RES1, RES2, RES3), + PAD_GPIO(160, GPIO_PZ1, POR_PD, Z1, VIMCLK2, SDMMC1, RES2, RES3), + PAD_NO_GPIO(161, GPIO_PZ2, POR_PD, SDMMC3, CCLA, RES2, RES3), + PAD_NO_GPIO(162, GPIO_PZ3, POR_PD, SDMMC3, RES1, RES2, RES3), + PAD_GPIO(163, GPIO_PZ4, POR_PD, Z4, SDMMC1, RES1, RES2, RES3), + PAD_NO_GPIO(164, GPIO_PZ5, POR_PD, SOC, RES1, RES2, RES3), +}; + +#endif /* __SOC_NVIDIA_TEGRA210_PINMUX_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/pmc.h b/src/soc/nvidia/tegra210/include/soc/pmc.h new file mode 100644 index 0000000000..77a7396d56 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/pmc.h @@ -0,0 +1,697 @@ +/* + * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA210_PMC_H_ +#define _TEGRA210_PMC_H_ + +#include <stdint.h> + +enum { + POWER_PARTID_CRAIL = 0, + POWER_PARTID_TD = 1, + POWER_PARTID_VE = 2, + POWER_PARTID_PCX = 3, + POWER_PARTID_C0L2 = 5, + POWER_PARTID_MPE = 6, + POWER_PARTID_HEG = 7, + POWER_PARTID_SAX = 8, + POWER_PARTID_CE1 = 9, + POWER_PARTID_CE2 = 10, + POWER_PARTID_CE3 = 11, + POWER_PARTID_CELP = 12, + POWER_PARTID_CE0 = 14, + POWER_PARTID_C0NC = 15, + POWER_PARTID_C1NC = 16, + POWER_PARTID_SOR = 17, + POWER_PARTID_DIS = 18, + POWER_PARTID_DISB = 19, + POWER_PARTID_XUSBA = 20, + POWER_PARTID_XUSBB = 21, + POWER_PARTID_XUSBC = 22, + POWER_PARTID_VIC = 23, + POWER_PARTID_IRAM = 24, + POWER_PARTID_NVDEC = 25, + POWER_PARTID_NVJPG = 26, + POWER_PARTID_APE = 27, + POWER_PARTID_DFD = 28, + POWER_PARTID_VE2 = 29, +}; + +struct tegra_pmc_regs { + u32 cntrl; + u32 sec_disable; + u32 pmc_swrst; + u32 wake_mask; + u32 wake_lvl; + u32 wake_status; + u32 sw_wake_status; + u32 dpd_pads_oride; + u32 dpd_sample; + u32 dpd_enable; + u32 pwrgate_timer_off; + u32 clamp_status; + u32 pwrgate_toggle; + u32 remove_clamping_cmd; + u32 pwrgate_status; + u32 pwrgood_timer; + u32 blink_timer; + u32 no_iopower; + u32 pwr_det; + u32 pwr_det_latch; + u32 scratch0; + u32 scratch1; + u32 scratch2; + u32 scratch3; + u32 scratch4; + u32 scratch5; + u32 scratch6; + u32 scratch7; + u32 scratch8; + u32 scratch9; + u32 scratch10; + u32 scratch11; + u32 scratch12; + u32 scratch13; + u32 scratch14; + u32 scratch15; + u32 scratch16; + u32 scratch17; + u32 scratch18; + u32 scratch19; + u32 odmdata; + u32 scratch21; + u32 scratch22; + u32 scratch23; + u32 secure_scratch0; + u32 secure_scratch1; + u32 secure_scratch2; + u32 secure_scratch3; + u32 secure_scratch4; + u32 secure_scratch5; + u32 cpupwrgood_timer; + u32 cpupwroff_timer; + u32 pg_mask; + u32 pg_mask_1; + u32 auto_wake_lvl; + u32 auto_wake_lvl_mask; + u32 wake_delay; + u32 pwr_det_val; + u32 ddr_pwr; + u32 usb_debounce_del; + u32 usb_a0; + u32 crypto_op; + u32 pllp_wb0_override; + u32 scratch24; + u32 scratch25; + u32 scratch26; + u32 scratch27; + u32 scratch28; + u32 scratch29; + u32 scratch30; + u32 scratch31; + u32 scratch32; + u32 scratch33; + u32 scratch34; + u32 scratch35; + u32 scratch36; + u32 scratch37; + u32 scratch38; + u32 scratch39; + u32 scratch40; + u32 scratch41; + u32 scratch42; + u32 bondout_mirror[3]; + u32 sys_33v_en; + u32 bondout_mirror_access; + u32 gate; + u32 wake2_mask; + u32 wake2_lvl; + u32 wake2_status; + u32 sw_wake2_status; + u32 auto_wake2_lvl_mask; + u32 pg_mask_2; + u32 pg_mask_ce1; + u32 pg_mask_ce2; + u32 pg_mask_ce3; + u32 pwrgate_timer_ce[7]; + u32 pcx_edpd_cntrl; + u32 osc_edpd_over; + u32 clk_out_cntrl; + u32 sata_pwrgt; + u32 sensor_ctrl; + u32 rst_status; + u32 io_dpd_req; + u32 io_dpd_status; + u32 io_dpd2_req; + u32 io_dpd2_status; + u32 sel_dpd_tim; + u32 vddp_sel; + u32 ddr_cfg; + u32 e_no_vttgen; + u8 _rsv0[4]; + u32 pllm_wb0_override_freq; + u32 test_pwrgate; + u32 pwrgate_timer_mult; + u32 dis_sel_dpd; + u32 utmip_uhsic_triggers; + u32 utmip_uhsic_saved_state; + u32 utmip_pad_cfg; + u32 utmip_term_pad_cfg; + u32 utmip_uhsic_sleep_cfg; + u32 utmip_uhsic_sleepwalk_cfg; + u32 utmip_sleepwalk_p[3]; + u32 uhsic_sleepwalk_p0; + u32 utmip_uhsic_status; + u32 utmip_uhsic_fake; + u32 bondout_mirror3[5 - 3]; + u32 secure_scratch6; + u32 secure_scratch7; + u32 scratch43; + u32 scratch44; + u32 scratch45; + u32 scratch46; + u32 scratch47; + u32 scratch48; + u32 scratch49; + u32 scratch50; + u32 scratch51; + u32 scratch52; + u32 scratch53; + u32 scratch54; + u32 scratch55; + u32 scratch0_eco; + u32 por_dpd_ctrl; + u32 scratch2_eco; + u32 utmip_uhsic_line_wakeup; + u32 utmip_bias_master_cntrl; + u32 utmip_master_config; + u32 td_pwrgate_inter_part_timer; + u32 utmip_uhsic2_triggers; + u32 utmip_uhsic2_saved_state; + u32 utmip_uhsic2_sleep_cfg; + u32 utmip_uhsic2_sleepwalk_cfg; + u32 uhsic2_sleepwalk_p1; + u32 utmip_uhsic2_status; + u32 utmip_uhsic2_fake; + u32 utmip_uhsic2_line_wakeup; + u32 utmip_master2_config; + u32 utmip_uhsic_rpd_cfg; + u32 pg_mask_ce0; + u32 pg_mask3[5 - 3]; + u32 pllm_wb0_override2; + u32 tsc_mult; + u32 cpu_vsense_override; + u32 glb_amap_cfg; + u32 sticky_bits; + u32 sec_disable2; + u32 weak_bias; + u32 reg_short; + u32 pg_mask_andor; + u8 _rsv1[0x2c]; + u32 secure_scratch8; /* offset 0x300 */ + u32 secure_scratch9; + u32 secure_scratch10; + u32 secure_scratch11; + u32 secure_scratch12; + u32 secure_scratch13; + u32 secure_scratch14; + u32 secure_scratch15; + u32 secure_scratch16; + u32 secure_scratch17; + u32 secure_scratch18; + u32 secure_scratch19; + u32 secure_scratch20; + u32 secure_scratch21; + u32 secure_scratch22; + u32 secure_scratch23; + u32 secure_scratch24; + u32 secure_scratch25; + u32 secure_scratch26; + u32 secure_scratch27; + u32 secure_scratch28; + u32 secure_scratch29; + u32 secure_scratch30; + u32 secure_scratch31; + u32 secure_scratch32; + u32 secure_scratch33; + u32 secure_scratch34; + u32 secure_scratch35; + u32 secure_scratch36; + u32 secure_scratch37; + u32 secure_scratch38; + u32 secure_scratch39; + u32 secure_scratch40; + u32 secure_scratch41; + u32 secure_scratch42; + u32 secure_scratch43; + u32 secure_scratch44; + u32 secure_scratch45; + u32 secure_scratch46; + u32 secure_scratch47; + u32 secure_scratch48; + u32 secure_scratch49; + u32 secure_scratch50; + u32 secure_scratch51; + u32 secure_scratch52; + u32 secure_scratch53; + u32 secure_scratch54; + u32 secure_scratch55; + u32 secure_scratch56; + u32 secure_scratch57; + u32 secure_scratch58; + u32 secure_scratch59; + u32 secure_scratch60; + u32 secure_scratch61; + u32 secure_scratch62; + u32 secure_scratch63; + u32 secure_scratch64; + u32 secure_scratch65; + u32 secure_scratch66; + u32 secure_scratch67; + u32 secure_scratch68; + u32 secure_scratch69; + u32 secure_scratch70; + u32 secure_scratch71; + u32 secure_scratch72; + u32 secure_scratch73; + u32 secure_scratch74; + u32 secure_scratch75; + u32 secure_scratch76; + u32 secure_scratch77; + u32 secure_scratch78; + u32 secure_scratch79; + u32 _rsv0x420[8]; + u32 cntrl2; /* 0x440 */ + u32 _rsv0x444[2]; + u32 event_counter; /* 0x44C */ + u32 fuse_control; + u32 scratch1_eco; + u32 _rsv0x458[1]; + u32 io_dpd3_req; /* 0x45C */ + u32 io_dpd3_status; + u32 io_dpd4_req; + u32 io_dpd4_status; + u32 _rsv0x46C[30]; + u32 ddr_cntrl; /* 0x4E4 */ + u32 _rsv0x4E8[70]; + u32 scratch56; /* 0x600 */ + u32 scratch57; + u32 scratch58; + u32 scratch59; + u32 scratch60; + u32 scratch61; + u32 scratch62; + u32 scratch63; + u32 scratch64; + u32 scratch65; + u32 scratch66; + u32 scratch67; + u32 scratch68; + u32 scratch69; + u32 scratch70; + u32 scratch71; + u32 scratch72; + u32 scratch73; + u32 scratch74; + u32 scratch75; + u32 scratch76; + u32 scratch77; + u32 scratch78; + u32 scratch79; + u32 scratch80; + u32 scratch81; + u32 scratch82; + u32 scratch83; + u32 scratch84; + u32 scratch85; + u32 scratch86; + u32 scratch87; + u32 scratch88; + u32 scratch89; + u32 scratch90; + u32 scratch91; + u32 scratch92; + u32 scratch93; + u32 scratch94; + u32 scratch95; + u32 scratch96; + u32 scratch97; + u32 scratch98; + u32 scratch99; + u32 scratch100; + u32 scratch101; + u32 scratch102; + u32 scratch103; + u32 scratch104; + u32 scratch105; + u32 scratch106; + u32 scratch107; + u32 scratch108; + u32 scratch109; + u32 scratch110; + u32 scratch111; + u32 scratch112; + u32 scratch113; + u32 scratch114; + u32 scratch115; + u32 scratch116; + u32 scratch117; + u32 scratch118; + u32 scratch119; + u32 scratch120; /* 0x700 */ + u32 scratch121; + u32 scratch122; + u32 scratch123; + u32 scratch124; + u32 scratch125; + u32 scratch126; + u32 scratch127; + u32 scratch128; + u32 scratch129; + u32 scratch130; + u32 scratch131; + u32 scratch132; + u32 scratch133; + u32 scratch134; + u32 scratch135; + u32 scratch136; + u32 scratch137; + u32 scratch138; + u32 scratch139; + u32 scratch140; + u32 scratch141; + u32 scratch142; + u32 scratch143; + u32 scratch144; + u32 scratch145; + u32 scratch146; + u32 scratch147; + u32 scratch148; + u32 scratch149; + u32 scratch150; + u32 scratch151; + u32 scratch152; + u32 scratch153; + u32 scratch154; + u32 scratch155; + u32 scratch156; + u32 scratch157; + u32 scratch158; + u32 scratch159; + u32 scratch160; + u32 scratch161; + u32 scratch162; + u32 scratch163; + u32 scratch164; + u32 scratch165; + u32 scratch166; + u32 scratch167; + u32 scratch168; + u32 scratch169; + u32 scratch170; + u32 scratch171; + u32 scratch172; + u32 scratch173; + u32 scratch174; + u32 scratch175; + u32 scratch176; + u32 scratch177; + u32 scratch178; + u32 scratch179; + u32 scratch180; + u32 scratch181; + u32 scratch182; + u32 scratch183; + u32 scratch184; + u32 scratch185; + u32 scratch186; + u32 scratch187; + u32 scratch188; + u32 scratch189; + u32 scratch190; + u32 scratch191; + u32 scratch192; + u32 scratch193; + u32 scratch194; + u32 scratch195; + u32 scratch196; + u32 scratch197; + u32 scratch198; + u32 scratch199; + u32 scratch200; + u32 scratch201; + u32 scratch202; + u32 scratch203; + u32 scratch204; + u32 scratch205; + u32 scratch206; + u32 scratch207; + u32 scratch208; + u32 scratch209; + u32 scratch210; + u32 scratch211; + u32 scratch212; + u32 scratch213; + u32 scratch214; + u32 scratch215; + u32 scratch216; + u32 scratch217; + u32 scratch218; + u32 scratch219; + u32 scratch220; + u32 scratch221; + u32 scratch222; + u32 scratch223; + u32 scratch224; + u32 scratch225; + u32 scratch226; + u32 scratch227; + u32 scratch228; + u32 scratch229; + u32 scratch230; + u32 scratch231; + u32 scratch232; + u32 scratch233; + u32 scratch234; + u32 scratch235; + u32 scratch236; + u32 scratch237; + u32 scratch238; + u32 scratch239; + u32 scratch240; + u32 scratch241; + u32 scratch242; + u32 scratch243; + u32 scratch244; + u32 scratch245; + u32 scratch246; + u32 scratch247; + u32 scratch248; + u32 scratch249; + u32 scratch250; + u32 scratch251; + u32 scratch252; + u32 scratch253; + u32 scratch254; + u32 scratch255; + u32 scratch256; + u32 scratch257; + u32 scratch258; + u32 scratch259; + u32 scratch260; + u32 scratch261; + u32 scratch262; + u32 scratch263; + u32 scratch264; + u32 scratch265; + u32 scratch266; + u32 scratch267; + u32 scratch268; + u32 scratch269; + u32 scratch270; + u32 scratch271; + u32 scratch272; + u32 scratch273; + u32 scratch274; + u32 scratch275; + u32 scratch276; + u32 scratch277; + u32 scratch278; + u32 scratch279; + u32 scratch280; + u32 scratch281; + u32 scratch282; + u32 scratch283; + u32 scratch284; + u32 scratch285; + u32 scratch286; + u32 scratch287; + u32 scratch288; + u32 scratch289; + u32 scratch290; + u32 scratch291; + u32 scratch292; + u32 scratch293; + u32 scratch294; + u32 scratch295; + u32 scratch296; + u32 scratch297; + u32 scratch298; + u32 scratch299; /* 0x9CC */ + u32 _rsv0x9D0[50]; + u32 secure_scratch80; /* 0xa98 */ + u32 secure_scratch81; + u32 secure_scratch82; + u32 secure_scratch83; + u32 secure_scratch84; + u32 secure_scratch85; + u32 secure_scratch86; + u32 secure_scratch87; + u32 secure_scratch88; + u32 secure_scratch89; + u32 secure_scratch90; + u32 secure_scratch91; + u32 secure_scratch92; + u32 secure_scratch93; + u32 secure_scratch94; + u32 secure_scratch95; + u32 secure_scratch96; + u32 secure_scratch97; + u32 secure_scratch98; + u32 secure_scratch99; + u32 secure_scratch100; + u32 secure_scratch101; + u32 secure_scratch102; + u32 secure_scratch103; + u32 secure_scratch104; + u32 secure_scratch105; + u32 secure_scratch106; + u32 secure_scratch107; + u32 secure_scratch108; + u32 secure_scratch109; + u32 secure_scratch110; + u32 secure_scratch111; + u32 secure_scratch112; + u32 secure_scratch113; + u32 secure_scratch114; + u32 secure_scratch115; + u32 secure_scratch116; + u32 secure_scratch117; + u32 secure_scratch118; + u32 secure_scratch119; +}; + +check_member(tegra_pmc_regs, secure_scratch119, 0xB34); + +enum { + PMC_RST_STATUS_SOURCE_MASK = 0x7, + PMC_RST_STATUS_SOURCE_POR = 0x0, + PMC_RST_STATUS_SOURCE_WATCHDOG = 0x1, + PMC_RST_STATUS_SOURCE_SENSOR = 0x2, + PMC_RST_STATUS_SOURCE_SW_MAIN = 0x3, + PMC_RST_STATUS_SOURCE_LP0 = 0x4, + PMC_RST_STATUS_NUM_SOURCES = 0x5, +}; + +enum { + PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f, + PMC_PWRGATE_TOGGLE_PARTID_SHIFT = 0, + PMC_PWRGATE_TOGGLE_START = 0x1 << 8 +}; + +enum { + PMC_CNTRL_KBC_CLK_DIS = 0x1 << 0, + PMC_CNTRL_RTC_CLK_DIS = 0x1 << 1, + PMC_CNTRL_RTC_RST = 0x1 << 2, + PMC_CNTRL_KBC_RST = 0x1 << 3, + PMC_CNTRL_MAIN_RST = 0x1 << 4, + PMC_CNTRL_LATCHWAKE_EN = 0x1 << 5, + PMC_CNTRL_GLITCHDET_DIS = 0x1 << 6, + PMC_CNTRL_BLINK_EN = 0x1 << 7, + PMC_CNTRL_PWRREQ_POLARITY = 0x1 << 8, + PMC_CNTRL_PWRREQ_OE = 0x1 << 9, + PMC_CNTRL_SYSCLK_POLARITY = 0x1 << 10, + PMC_CNTRL_SYSCLK_OE = 0x1 << 11, + PMC_CNTRL_PWRGATE_DIS = 0x1 << 12, + PMC_CNTRL_AOINIT = 0x1 << 13, + PMC_CNTRL_SIDE_EFFECT_LP0 = 0x1 << 14, + PMC_CNTRL_CPUPWRREQ_POLARITY = 0x1 << 15, + PMC_CNTRL_CPUPWRREQ_OE = 0x1 << 16, + PMC_CNTRL_INTR_POLARITY = 0x1 << 17, + PMC_CNTRL_FUSE_OVERRIDE = 0x1 << 18, + PMC_CNTRL_CPUPWRGOOD_EN = 0x1 << 19, + PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT = 20, + PMC_CNTRL_CPUPWRGOOD_SEL_MASK = + 0x3 << PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT +}; + +enum { + PMC_DDR_PWR_EMMC_MASK = 1 << 1, + PMC_DDR_PWR_VAL_MASK = 1 << 0, +}; + +enum { + PMC_DDR_CFG_PKG_MASK = 1 << 0, + PMC_DDR_CFG_IF_MASK = 1 << 1, + PMC_DDR_CFG_XM0_RESET_TRI_MASK = 1 << 12, + PMC_DDR_CFG_XM0_RESET_DPDIO_MASK = 1 << 13, +}; + +enum { + PMC_NO_IOPOWER_MEM_MASK = 1 << 7, + PMC_NO_IOPOWER_MEM_COMP_MASK = 1 << 16, +}; + +enum { + PMC_POR_DPD_CTRL_MEM0_ADDR0_CLK_SEL_DPD_MASK = 1 << 0, + PMC_POR_DPD_CTRL_MEM0_ADDR1_CLK_SEL_DPD_MASK = 1 << 1, + PMC_POR_DPD_CTRL_MEM0_HOLD_CKE_LOW_OVR_MASK = 1 << 31, +}; + +enum { + PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12 +}; + +enum { + PMC_OSC_EDPD_OVER_XOFS_SHIFT = 1, + PMC_OSC_EDPD_OVER_XOFS_MASK = + 0x3f << PMC_OSC_EDPD_OVER_XOFS_SHIFT +}; + +enum { + PMC_CMD_HOLD_LOW_BR00_11_MASK = 0x0007FF80, + DPD_OFF = 1 << 30, + DPD_ON = 2 << 30, +}; + +enum { + PMC_GPIO_RAIL_AO_SHIFT = 21, + PMC_GPIO_RAIL_AO_MASK = (1 << PMC_GPIO_RAIL_AO_SHIFT), + PMC_GPIO_RAIL_AO_DISABLE = (0 << PMC_GPIO_RAIL_AO_SHIFT), + PMC_GPIO_RAIL_AO_ENABLE = (1 << PMC_GPIO_RAIL_AO_SHIFT), + + PMC_AUDIO_RAIL_AO_SHIFT = 18, + PMC_AUDIO_RAIL_AO_MASK = (1 << PMC_AUDIO_RAIL_AO_SHIFT), + PMC_AUDIO_RAIL_AO_DISABLE = (0 << PMC_AUDIO_RAIL_AO_SHIFT), + PMC_AUDIO_RAIL_AO_ENABLE = (1 << PMC_AUDIO_RAIL_AO_SHIFT), + + PMC_SDMMC3_RAIL_AO_SHIFT = 13, + PMC_SDMMC3_RAIL_AO_MASK = (1 << PMC_SDMMC3_RAIL_AO_SHIFT), + PMC_SDMMC3_RAIL_AO_DISABLE = (0 << PMC_SDMMC3_RAIL_AO_SHIFT), + PMC_SDMMC3_RAIL_AO_ENABLE = (1 << PMC_SDMMC3_RAIL_AO_SHIFT), +}; + +#endif /* _TEGRA210_PMC_H_ */ diff --git a/src/soc/nvidia/tegra210/include/soc/power.h b/src/soc/nvidia/tegra210/include/soc/power.h new file mode 100644 index 0000000000..c40609666a --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/power.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_POWER_H__ +#define __SOC_NVIDIA_TEGRA210_POWER_H__ + +#include <soc/pmc.h> + +void power_ungate_partition(uint32_t id); +void power_gate_partition(uint32_t id); + +uint8_t pmc_rst_status(void); +void pmc_print_rst_status(void); +void remove_clamps(int id); +void pmc_override_pwr_det(uint32_t bits, uint32_t override); + +#endif /* __SOC_NVIDIA_TEGRA210_POWER_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/romstage.h b/src/soc/nvidia/tegra210/include/soc/romstage.h new file mode 100644 index 0000000000..d4ab982382 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/romstage.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_SOC_ROMSTAGE_H__ +#define __SOC_NVIDIA_TEGRA210_SOC_ROMSTAGE_H__ + +void romstage(void); +void romstage_mainboard_init(void); + +void mainboard_configure_pmc(void); +void mainboard_enable_vdd_cpu(void); + +#endif /* __SOC_NVIDIA_TEGRA210_SOC_ROMSTAGE_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/sdram.h b/src/soc/nvidia/tegra210/include/soc/sdram.h new file mode 100644 index 0000000000..a8dec820c5 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/sdram.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_H__ +#define __SOC_NVIDIA_TEGRA210_SDRAM_H__ + +#include <soc/sdram_param.h> + +uint32_t sdram_get_ram_code(void); +void sdram_init(const struct sdram_params *param); + +/* Save params to PMC scratch registers for use by BootROM on LP0 resume. */ +void sdram_lp0_save_params(const struct sdram_params *sdram); + +#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_configs.h b/src/soc/nvidia/tegra210/include/soc/sdram_configs.h new file mode 100644 index 0000000000..905ff9c50f --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/sdram_configs.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_CONFIGS_H__ +#define __SOC_NVIDIA_TEGRA210_SDRAM_CONFIGS_H__ + +#include <soc/sdram.h> + +/* Loads SDRAM configurations for current system. */ +const struct sdram_params *get_sdram_config(void); + +#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_CONFIGS_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/sdram_param.h b/src/soc/nvidia/tegra210/include/soc/sdram_param.h new file mode 100644 index 0000000000..018101efe8 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/sdram_param.h @@ -0,0 +1,979 @@ +/* + * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * See file CREDITS for list of people who contributed to this + * project. + */ + +/** + * Defines the SDRAM parameter structure. + * + * Note that PLLM is used by EMC. The field names are in camel case to ease + * directly converting BCT config files (*.cfg) into C structure. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ +#define __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ + +#include <stddef.h> +#include <stdint.h> + +enum { + /* Specifies the memory type to be undefined */ + NvBootMemoryType_None = 0, + + /* Specifies the memory type to be DDR SDRAM */ + NvBootMemoryType_Ddr = 0, + + /* Specifies the memory type to be LPDDR SDRAM */ + NvBootMemoryType_LpDdr = 0, + + /* Specifies the memory type to be DDR2 SDRAM */ + NvBootMemoryType_Ddr2 = 0, + + /* Specifies the memory type to be LPDDR2 SDRAM */ + NvBootMemoryType_LpDdr2, + + /* Specifies the memory type to be DDR3 SDRAM */ + NvBootMemoryType_Ddr3, + + /* Specifies the memory type to be LPDDR4 SDRAM */ + NvBootMemoryType_LpDdr4, + + NvBootMemoryType_Num, + + /* Specifies an entry in the ram_code table that's not in use */ + NvBootMemoryType_Unused = 0X7FFFFFF, +}; + +enum { + BOOT_ROM_PATCH_CONTROL_ENABLE_MASK = 0x1 << 31, + BOOT_ROM_PATCH_CONTROL_OFFSET_SHIFT = 0, + BOOT_ROM_PATCH_CONTROL_OFFSET_MASK = 0x7FFFFFFF << 0, + BOOT_ROM_PATCH_CONTROL_BASE_ADDRESS = 0x70000000, + + EMC_ZCAL_WARM_COLD_BOOT_ENABLES_COLDBOOT_MASK = 1 << 0, +}; + +/** + * Defines the SDRAM parameter structure + */ +struct sdram_params { + + /* Specifies the type of memory device */ + uint32_t MemoryType; + + /* MC/EMC clock source configuration */ + + /* Specifies the M value for PllM */ + uint32_t PllMInputDivider; + /* Specifies the N value for PllM */ + uint32_t PllMFeedbackDivider; + /* Specifies the time to wait for PLLM to lock (in microseconds) */ + uint32_t PllMStableTime; + /* Specifies misc. control bits */ + uint32_t PllMSetupControl; + /* Specifies the P value for PLLM */ + uint32_t PllMPostDivider; + /* Specifies value for Charge Pump Gain Control */ + uint32_t PllMKCP; + /* Specifies VCO gain */ + uint32_t PllMKVCO; + /* Spare BCT param */ + uint32_t EmcBctSpare0; + /* Spare BCT param */ + uint32_t EmcBctSpare1; + /* Spare BCT param */ + uint32_t EmcBctSpare2; + /* Spare BCT param */ + uint32_t EmcBctSpare3; + /* Spare BCT param */ + uint32_t EmcBctSpare4; + /* Spare BCT param */ + uint32_t EmcBctSpare5; + /* Spare BCT param */ + uint32_t EmcBctSpare6; + /* Spare BCT param */ + uint32_t EmcBctSpare7; + /* Spare BCT param */ + uint32_t EmcBctSpare8; + /* Spare BCT param */ + uint32_t EmcBctSpare9; + /* Spare BCT param */ + uint32_t EmcBctSpare10; + /* Spare BCT param */ + uint32_t EmcBctSpare11; + /* Spare BCT param */ + uint32_t EmcBctSpare12; + /* Spare BCT param */ + uint32_t EmcBctSpare13; + + /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ + uint32_t EmcClockSource; + uint32_t EmcClockSourceDll; + + /* Defines possible override for PLLLM_MISC2 */ + uint32_t ClkRstControllerPllmMisc2Override; + /* enables override for PLLLM_MISC2 */ + uint32_t ClkRstControllerPllmMisc2OverrideEnable; + /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ + uint32_t ClearClk2Mc1; + + /* Auto-calibration of EMC pads */ + + /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ + uint32_t EmcAutoCalInterval; + /* + * Specifies the value for EMC_AUTO_CAL_CONFIG + * Note: Trigger bits are set by the SDRAM code. + */ + uint32_t EmcAutoCalConfig; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ + uint32_t EmcAutoCalConfig2; + + /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ + uint32_t EmcAutoCalConfig3; + + /* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */ + uint32_t EmcAutoCalConfig4; + uint32_t EmcAutoCalConfig5; + uint32_t EmcAutoCalConfig6; + uint32_t EmcAutoCalConfig7; + uint32_t EmcAutoCalConfig8; + + /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ + uint32_t EmcAutoCalVrefSel0; + uint32_t EmcAutoCalVrefSel1; + + /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ + uint32_t EmcAutoCalChannel; + + /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ + uint32_t EmcPmacroAutocalCfg0; + uint32_t EmcPmacroAutocalCfg1; + uint32_t EmcPmacroAutocalCfg2; + uint32_t EmcPmacroRxTerm; + uint32_t EmcPmacroDqTxDrv; + uint32_t EmcPmacroCaTxDrv; + uint32_t EmcPmacroCmdTxDrv; + uint32_t EmcPmacroAutocalCfgCommon; + uint32_t EmcPmacroZctrl; + + /* + * Specifies the time for the calibration + * to stabilize (in microseconds) + */ + uint32_t EmcAutoCalWait; + + uint32_t EmcXm2CompPadCtrl; + uint32_t EmcXm2CompPadCtrl2; + uint32_t EmcXm2CompPadCtrl3; + + /* + * DRAM size information + * Specifies the value for EMC_ADR_CFG + */ + uint32_t EmcAdrCfg; + + /* + * Specifies the time to wait after asserting pin + * CKE (in microseconds) + */ + uint32_t EmcPinProgramWait; + /* Specifies the extra delay before/after pin RESET/CKE command */ + uint32_t EmcPinExtraWait; + + uint32_t EmcPinGpioEn; + uint32_t EmcPinGpio; + + /* + * Specifies the extra delay after the first writing + * of EMC_TIMING_CONTROL + */ + uint32_t EmcTimingControlWait; + + /* Timing parameters required for the SDRAM */ + + /* Specifies the value for EMC_RC */ + uint32_t EmcRc; + /* Specifies the value for EMC_RFC */ + uint32_t EmcRfc; + /* Specifies the value for EMC_RFC_PB */ + uint32_t EmcRfcPb; + /* Specifies the value for EMC_RFC_CTRL2 */ + uint32_t EmcRefctrl2; + /* Specifies the value for EMC_RFC_SLR */ + uint32_t EmcRfcSlr; + /* Specifies the value for EMC_RAS */ + uint32_t EmcRas; + /* Specifies the value for EMC_RP */ + uint32_t EmcRp; + /* Specifies the value for EMC_R2R */ + uint32_t EmcR2r; + /* Specifies the value for EMC_W2W */ + uint32_t EmcW2w; + /* Specifies the value for EMC_R2W */ + uint32_t EmcR2w; + /* Specifies the value for EMC_W2R */ + uint32_t EmcW2r; + /* Specifies the value for EMC_R2P */ + uint32_t EmcR2p; + /* Specifies the value for EMC_W2P */ + uint32_t EmcW2p; + + uint32_t EmcTppd; + uint32_t EmcCcdmw; + + /* Specifies the value for EMC_RD_RCD */ + uint32_t EmcRdRcd; + /* Specifies the value for EMC_WR_RCD */ + uint32_t EmcWrRcd; + /* Specifies the value for EMC_RRD */ + uint32_t EmcRrd; + /* Specifies the value for EMC_REXT */ + uint32_t EmcRext; + /* Specifies the value for EMC_WEXT */ + uint32_t EmcWext; + /* Specifies the value for EMC_WDV */ + uint32_t EmcWdv; + + uint32_t EmcWdvChk; + uint32_t EmcWsv; + uint32_t EmcWev; + + /* Specifies the value for EMC_WDV_MASK */ + uint32_t EmcWdvMask; + + uint32_t EmcWsDuration; + uint32_t EmcWeDuration; + + /* Specifies the value for EMC_QUSE */ + uint32_t EmcQUse; + /* Specifies the value for EMC_QUSE_WIDTH */ + uint32_t EmcQuseWidth; + /* Specifies the value for EMC_IBDLY */ + uint32_t EmcIbdly; + /* Specifies the value for EMC_OBDLY */ + uint32_t EmcObdly; + /* Specifies the value for EMC_EINPUT */ + uint32_t EmcEInput; + /* Specifies the value for EMC_EINPUT_DURATION */ + uint32_t EmcEInputDuration; + /* Specifies the value for EMC_PUTERM_EXTRA */ + uint32_t EmcPutermExtra; + /* Specifies the value for EMC_PUTERM_WIDTH */ + uint32_t EmcPutermWidth; + /* Specifies the value for EMC_PUTERM_ADJ */ + uint32_t EmcPutermAdj; + + /* Specifies the value for EMC_QRST */ + uint32_t EmcQRst; + /* Specifies the value for EMC_QSAFE */ + uint32_t EmcQSafe; + /* Specifies the value for EMC_RDV */ + uint32_t EmcRdv; + /* Specifies the value for EMC_RDV_MASK */ + uint32_t EmcRdvMask; + /* Specifies the value for EMC_RDV_EARLY */ + uint32_t EmcRdvEarly; + /* Specifies the value for EMC_RDV_EARLY_MASK */ + uint32_t EmcRdvEarlyMask; + /* Specifies the value for EMC_QPOP */ + uint32_t EmcQpop; + + /* Specifies the value for EMC_REFRESH */ + uint32_t EmcRefresh; + /* Specifies the value for EMC_BURST_REFRESH_NUM */ + uint32_t EmcBurstRefreshNum; + /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ + uint32_t EmcPreRefreshReqCnt; + /* Specifies the value for EMC_PDEX2WR */ + uint32_t EmcPdEx2Wr; + /* Specifies the value for EMC_PDEX2RD */ + uint32_t EmcPdEx2Rd; + /* Specifies the value for EMC_PCHG2PDEN */ + uint32_t EmcPChg2Pden; + /* Specifies the value for EMC_ACT2PDEN */ + uint32_t EmcAct2Pden; + /* Specifies the value for EMC_AR2PDEN */ + uint32_t EmcAr2Pden; + /* Specifies the value for EMC_RW2PDEN */ + uint32_t EmcRw2Pden; + /* Specifies the value for EMC_CKE2PDEN */ + uint32_t EmcCke2Pden; + /* Specifies the value for EMC_PDEX2CKE */ + uint32_t EmcPdex2Cke; + /* Specifies the value for EMC_PDEX2MRR */ + uint32_t EmcPdex2Mrr; + /* Specifies the value for EMC_TXSR */ + uint32_t EmcTxsr; + /* Specifies the value for EMC_TXSRDLL */ + uint32_t EmcTxsrDll; + /* Specifies the value for EMC_TCKE */ + uint32_t EmcTcke; + /* Specifies the value for EMC_TCKESR */ + uint32_t EmcTckesr; + /* Specifies the value for EMC_TPD */ + uint32_t EmcTpd; + /* Specifies the value for EMC_TFAW */ + uint32_t EmcTfaw; + /* Specifies the value for EMC_TRPAB */ + uint32_t EmcTrpab; + /* Specifies the value for EMC_TCLKSTABLE */ + uint32_t EmcTClkStable; + /* Specifies the value for EMC_TCLKSTOP */ + uint32_t EmcTClkStop; + /* Specifies the value for EMC_TREFBW */ + uint32_t EmcTRefBw; + + /* FBIO configuration values */ + + /* Specifies the value for EMC_FBIO_CFG5 */ + uint32_t EmcFbioCfg5; + /* Specifies the value for EMC_FBIO_CFG7 */ + uint32_t EmcFbioCfg7; + /* Specifies the value for EMC_FBIO_CFG8 */ + uint32_t EmcFbioCfg8; + + /* Command mapping for CMD brick 0 */ + uint32_t EmcCmdMappingCmd0_0; + uint32_t EmcCmdMappingCmd0_1; + uint32_t EmcCmdMappingCmd0_2; + uint32_t EmcCmdMappingCmd1_0; + uint32_t EmcCmdMappingCmd1_1; + uint32_t EmcCmdMappingCmd1_2; + uint32_t EmcCmdMappingCmd2_0; + uint32_t EmcCmdMappingCmd2_1; + uint32_t EmcCmdMappingCmd2_2; + uint32_t EmcCmdMappingCmd3_0; + uint32_t EmcCmdMappingCmd3_1; + uint32_t EmcCmdMappingCmd3_2; + uint32_t EmcCmdMappingByte; + + /* Specifies the value for EMC_FBIO_SPARE */ + uint32_t EmcFbioSpare; + + /* Specifies the value for EMC_CFG_RSV */ + uint32_t EmcCfgRsv; + + /* MRS command values */ + + /* Specifies the value for EMC_MRS */ + uint32_t EmcMrs; + /* Specifies the MP0 command to initialize mode registers */ + uint32_t EmcEmrs; + /* Specifies the MP2 command to initialize mode registers */ + uint32_t EmcEmrs2; + /* Specifies the MP3 command to initialize mode registers */ + uint32_t EmcEmrs3; + /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ + uint32_t EmcMrw1; + /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ + uint32_t EmcMrw2; + /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ + uint32_t EmcMrw3; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t EmcMrw4; + /* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */ + uint32_t EmcMrw6; + /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ + uint32_t EmcMrw8; + /* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */ + uint32_t EmcMrw9; + /* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */ + uint32_t EmcMrw10; + /* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */ + uint32_t EmcMrw12; + /* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */ + uint32_t EmcMrw13; + /* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */ + uint32_t EmcMrw14; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at cold boot + */ + uint32_t EmcMrwExtra; + /* + * Specifies the programming to extra LPDDR2 Mode Register + * at warm boot + */ + uint32_t EmcWarmBootMrwExtra; + /* + * Specify the enable of extra Mode Register programming at + * warm boot + */ + uint32_t EmcWarmBootExtraModeRegWriteEnable; + /* + * Specify the enable of extra Mode Register programming at + * cold boot + */ + uint32_t EmcExtraModeRegWriteEnable; + + /* Specifies the EMC_MRW reset command value */ + uint32_t EmcMrwResetCommand; + /* Specifies the EMC Reset wait time (in microseconds) */ + uint32_t EmcMrwResetNInitWait; + /* Specifies the value for EMC_MRS_WAIT_CNT */ + uint32_t EmcMrsWaitCnt; + /* Specifies the value for EMC_MRS_WAIT_CNT2 */ + uint32_t EmcMrsWaitCnt2; + + /* EMC miscellaneous configurations */ + + /* Specifies the value for EMC_CFG */ + uint32_t EmcCfg; + /* Specifies the value for EMC_CFG_2 */ + uint32_t EmcCfg2; + /* Specifies the pipe bypass controls */ + uint32_t EmcCfgPipe; + uint32_t EmcCfgPipeClk; + uint32_t EmcFdpdCtrlCmdNoRamp; + uint32_t EmcCfgUpdate; + + /* Specifies the value for EMC_DBG */ + uint32_t EmcDbg; + uint32_t EmcDbgWriteMux; + + /* Specifies the value for EMC_CMDQ */ + uint32_t EmcCmdQ; + /* Specifies the value for EMC_MC2EMCQ */ + uint32_t EmcMc2EmcQ; + /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ + uint32_t EmcDynSelfRefControl; + + /* Specifies the value for MEM_INIT_DONE */ + uint32_t AhbArbitrationXbarCtrlMemInitDone; + + /* Specifies the value for EMC_CFG_DIG_DLL */ + uint32_t EmcCfgDigDll; + uint32_t EmcCfgDigDll_1; + /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ + uint32_t EmcCfgDigDllPeriod; + /* Specifies the value of *DEV_SELECTN of various EMC registers */ + uint32_t EmcDevSelect; + + /* Specifies the value for EMC_SEL_DPD_CTRL */ + uint32_t EmcSelDpdCtrl; + + /* Pads trimmer delays */ + uint32_t EmcFdpdCtrlDq; + uint32_t EmcFdpdCtrlCmd; + uint32_t EmcPmacroIbVrefDq_0; + uint32_t EmcPmacroIbVrefDq_1; + uint32_t EmcPmacroIbVrefDqs_0; + uint32_t EmcPmacroIbVrefDqs_1; + uint32_t EmcPmacroIbRxrt; + uint32_t EmcCfgPipe1; + uint32_t EmcCfgPipe2; + + /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ + uint32_t EmcPmacroQuseDdllRank0_0; + uint32_t EmcPmacroQuseDdllRank0_1; + uint32_t EmcPmacroQuseDdllRank0_2; + uint32_t EmcPmacroQuseDdllRank0_3; + uint32_t EmcPmacroQuseDdllRank0_4; + uint32_t EmcPmacroQuseDdllRank0_5; + uint32_t EmcPmacroQuseDdllRank1_0; + uint32_t EmcPmacroQuseDdllRank1_1; + uint32_t EmcPmacroQuseDdllRank1_2; + uint32_t EmcPmacroQuseDdllRank1_3; + uint32_t EmcPmacroQuseDdllRank1_4; + uint32_t EmcPmacroQuseDdllRank1_5; + + uint32_t EmcPmacroObDdllLongDqRank0_0; + uint32_t EmcPmacroObDdllLongDqRank0_1; + uint32_t EmcPmacroObDdllLongDqRank0_2; + uint32_t EmcPmacroObDdllLongDqRank0_3; + uint32_t EmcPmacroObDdllLongDqRank0_4; + uint32_t EmcPmacroObDdllLongDqRank0_5; + uint32_t EmcPmacroObDdllLongDqRank1_0; + uint32_t EmcPmacroObDdllLongDqRank1_1; + uint32_t EmcPmacroObDdllLongDqRank1_2; + uint32_t EmcPmacroObDdllLongDqRank1_3; + uint32_t EmcPmacroObDdllLongDqRank1_4; + uint32_t EmcPmacroObDdllLongDqRank1_5; + + uint32_t EmcPmacroObDdllLongDqsRank0_0; + uint32_t EmcPmacroObDdllLongDqsRank0_1; + uint32_t EmcPmacroObDdllLongDqsRank0_2; + uint32_t EmcPmacroObDdllLongDqsRank0_3; + uint32_t EmcPmacroObDdllLongDqsRank0_4; + uint32_t EmcPmacroObDdllLongDqsRank0_5; + uint32_t EmcPmacroObDdllLongDqsRank1_0; + uint32_t EmcPmacroObDdllLongDqsRank1_1; + uint32_t EmcPmacroObDdllLongDqsRank1_2; + uint32_t EmcPmacroObDdllLongDqsRank1_3; + uint32_t EmcPmacroObDdllLongDqsRank1_4; + uint32_t EmcPmacroObDdllLongDqsRank1_5; + + uint32_t EmcPmacroIbDdllLongDqsRank0_0; + uint32_t EmcPmacroIbDdllLongDqsRank0_1; + uint32_t EmcPmacroIbDdllLongDqsRank0_2; + uint32_t EmcPmacroIbDdllLongDqsRank0_3; + uint32_t EmcPmacroIbDdllLongDqsRank1_0; + uint32_t EmcPmacroIbDdllLongDqsRank1_1; + uint32_t EmcPmacroIbDdllLongDqsRank1_2; + uint32_t EmcPmacroIbDdllLongDqsRank1_3; + + uint32_t EmcPmacroDdllLongCmd_0; + uint32_t EmcPmacroDdllLongCmd_1; + uint32_t EmcPmacroDdllLongCmd_2; + uint32_t EmcPmacroDdllLongCmd_3; + uint32_t EmcPmacroDdllLongCmd_4; + uint32_t EmcPmacroDdllShortCmd_0; + uint32_t EmcPmacroDdllShortCmd_1; + uint32_t EmcPmacroDdllShortCmd_2; + + /* + * Specifies the delay after asserting CKE pin during a WarmBoot0 + * sequence (in microseconds) + */ + uint32_t WarmBootWait; + + /* Specifies the value for EMC_ODT_WRITE */ + uint32_t EmcOdtWrite; + + /* Periodic ZQ calibration */ + + /* + * Specifies the value for EMC_ZCAL_INTERVAL + * Value 0 disables ZQ calibration + */ + uint32_t EmcZcalInterval; + /* Specifies the value for EMC_ZCAL_WAIT_CNT */ + uint32_t EmcZcalWaitCnt; + /* Specifies the value for EMC_ZCAL_MRW_CMD */ + uint32_t EmcZcalMrwCmd; + + /* DRAM initialization sequence flow control */ + + /* Specifies the MRS command value for resetting DLL */ + uint32_t EmcMrsResetDll; + /* Specifies the command for ZQ initialization of device 0 */ + uint32_t EmcZcalInitDev0; + /* Specifies the command for ZQ initialization of device 1 */ + uint32_t EmcZcalInitDev1; + /* + * Specifies the wait time after programming a ZQ initialization + * command (in microseconds) + */ + uint32_t EmcZcalInitWait; + /* + * Specifies the enable for ZQ calibration at cold boot [bit 0] + * and warm boot [bit 1] + */ + uint32_t EmcZcalWarmColdBootEnables; + + /* + * Specifies the MRW command to LPDDR2 for ZQ calibration + * on warmboot + */ + /* Is issued to both devices separately */ + uint32_t EmcMrwLpddr2ZcalWarmBoot; + /* + * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot + * Is issued to both devices separately + */ + uint32_t EmcZqCalDdr3WarmBoot; + uint32_t EmcZqCalLpDdr4WarmBoot; + /* + * Specifies the wait time for ZQ calibration on warmboot + * (in microseconds) + */ + uint32_t EmcZcalWarmBootWait; + /* + * Specifies the enable for DRAM Mode Register programming + * at warm boot + */ + uint32_t EmcMrsWarmBootEnable; + /* + * Specifies the wait time after sending an MRS DLL reset command + * in microseconds) + */ + uint32_t EmcMrsResetDllWait; + /* Specifies the extra MRS command to initialize mode registers */ + uint32_t EmcMrsExtra; + /* Specifies the extra MRS command at warm boot */ + uint32_t EmcWarmBootMrsExtra; + /* Specifies the EMRS command to enable the DDR2 DLL */ + uint32_t EmcEmrsDdr2DllEnable; + /* Specifies the MRS command to reset the DDR2 DLL */ + uint32_t EmcMrsDdr2DllReset; + /* Specifies the EMRS command to set OCD calibration */ + uint32_t EmcEmrsDdr2OcdCalib; + /* + * Specifies the wait between initializing DDR and setting OCD + * calibration (in microseconds) + */ + uint32_t EmcDdr2Wait; + /* Specifies the value for EMC_CLKEN_OVERRIDE */ + uint32_t EmcClkenOverride; + + /* + * Specifies LOG2 of the extra refresh numbers after booting + * Program 0 to disable + */ + uint32_t EmcExtraRefreshNum; + /* Specifies the master override for all EMC clocks */ + uint32_t EmcClkenOverrideAllWarmBoot; + /* Specifies the master override for all MC clocks */ + uint32_t McClkenOverrideAllWarmBoot; + /* Specifies digital dll period, choosing between 4 to 64 ms */ + uint32_t EmcCfgDigDllPeriodWarmBoot; + + /* Pad controls */ + + /* Specifies the value for PMC_VDDP_SEL */ + uint32_t PmcVddpSel; + /* Specifies the wait time after programming PMC_VDDP_SEL */ + uint32_t PmcVddpSelWait; + /* Specifies the value for PMC_DDR_PWR */ + uint32_t PmcDdrPwr; + /* Specifies the value for PMC_DDR_CFG */ + uint32_t PmcDdrCfg; + /* Specifies the value for PMC_IO_DPD3_REQ */ + uint32_t PmcIoDpd3Req; + /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ + uint32_t PmcIoDpd3ReqWait; + uint32_t PmcIoDpd4ReqWait; + + /* Specifies the value for PMC_REG_SHORT */ + uint32_t PmcRegShort; + /* Specifies the value for PMC_NO_IOPOWER */ + uint32_t PmcNoIoPower; + + uint32_t PmcDdrCntrlWait; + uint32_t PmcDdrCntrl; + + /* Specifies the value for EMC_ACPD_CONTROL */ + uint32_t EmcAcpdControl; + + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ + uint32_t EmcSwizzleRank0ByteCfg; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ + uint32_t EmcSwizzleRank0Byte0; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ + uint32_t EmcSwizzleRank0Byte1; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ + uint32_t EmcSwizzleRank0Byte2; + /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ + uint32_t EmcSwizzleRank0Byte3; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ + uint32_t EmcSwizzleRank1ByteCfg; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ + uint32_t EmcSwizzleRank1Byte0; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ + uint32_t EmcSwizzleRank1Byte1; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ + uint32_t EmcSwizzleRank1Byte2; + /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ + uint32_t EmcSwizzleRank1Byte3; + + /* Specifies the value for EMC_TXDSRVTTGEN */ + uint32_t EmcTxdsrvttgen; + + /* Specifies the value for EMC_DATA_BRLSHFT_0 */ + uint32_t EmcDataBrlshft0; + uint32_t EmcDataBrlshft1; + + uint32_t EmcDqsBrlshft0; + uint32_t EmcDqsBrlshft1; + + uint32_t EmcCmdBrlshft0; + uint32_t EmcCmdBrlshft1; + uint32_t EmcCmdBrlshft2; + uint32_t EmcCmdBrlshft3; + + uint32_t EmcQuseBrlshft0; + uint32_t EmcQuseBrlshft1; + uint32_t EmcQuseBrlshft2; + uint32_t EmcQuseBrlshft3; + + uint32_t EmcDllCfg0; + uint32_t EmcDllCfg1; + + uint32_t EmcPmcScratch1; + uint32_t EmcPmcScratch2; + uint32_t EmcPmcScratch3; + + uint32_t EmcPmacroPadCfgCtrl; + + uint32_t EmcPmacroVttgenCtrl0; + uint32_t EmcPmacroVttgenCtrl1; + uint32_t EmcPmacroVttgenCtrl2; + + uint32_t EmcPmacroBrickCtrlRfu1; + uint32_t EmcPmacroCmdBrickCtrlFdpd; + uint32_t EmcPmacroBrickCtrlRfu2; + uint32_t EmcPmacroDataBrickCtrlFdpd; + uint32_t EmcPmacroBgBiasCtrl0; + uint32_t EmcPmacroDataPadRxCtrl; + uint32_t EmcPmacroCmdPadRxCtrl; + uint32_t EmcPmacroDataRxTermMode; + uint32_t EmcPmacroCmdRxTermMode; + uint32_t EmcPmacroDataPadTxCtrl; + uint32_t EmcPmacroCommonPadTxCtrl; + uint32_t EmcPmacroCmdPadTxCtrl; + uint32_t EmcCfg3; + + uint32_t EmcPmacroTxPwrd0; + uint32_t EmcPmacroTxPwrd1; + uint32_t EmcPmacroTxPwrd2; + uint32_t EmcPmacroTxPwrd3; + uint32_t EmcPmacroTxPwrd4; + uint32_t EmcPmacroTxPwrd5; + + uint32_t EmcConfigSampleDelay; + + uint32_t EmcPmacroBrickMapping0; + uint32_t EmcPmacroBrickMapping1; + uint32_t EmcPmacroBrickMapping2; + + uint32_t EmcPmacroTxSelClkSrc0; + uint32_t EmcPmacroTxSelClkSrc1; + uint32_t EmcPmacroTxSelClkSrc2; + uint32_t EmcPmacroTxSelClkSrc3; + uint32_t EmcPmacroTxSelClkSrc4; + uint32_t EmcPmacroTxSelClkSrc5; + + uint32_t EmcPmacroDdllBypass; + + uint32_t EmcPmacroDdllPwrd0; + uint32_t EmcPmacroDdllPwrd1; + uint32_t EmcPmacroDdllPwrd2; + + uint32_t EmcPmacroCmdCtrl0; + uint32_t EmcPmacroCmdCtrl1; + uint32_t EmcPmacroCmdCtrl2; + + /* DRAM size information */ + + /* Specifies the value for MC_EMEM_ADR_CFG */ + uint32_t McEmemAdrCfg; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ + uint32_t McEmemAdrCfgDev0; + /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ + uint32_t McEmemAdrCfgDev1; + uint32_t McEmemAdrCfgChannelMask; + + /* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */ + uint32_t McEmemAdrCfgBankMask0; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ + uint32_t McEmemAdrCfgBankMask1; + /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ + uint32_t McEmemAdrCfgBankMask2; + + /* + * Specifies the value for MC_EMEM_CFG which holds the external memory + * size (in KBytes) + */ + uint32_t McEmemCfg; + + /* MC arbitration configuration */ + + /* Specifies the value for MC_EMEM_ARB_CFG */ + uint32_t McEmemArbCfg; + /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ + uint32_t McEmemArbOutstandingReq; + + uint32_t McEmemArbRefpbHpCtrl; + uint32_t McEmemArbRefpbBankCtrl; + + /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ + uint32_t McEmemArbTimingRcd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ + uint32_t McEmemArbTimingRp; + /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ + uint32_t McEmemArbTimingRc; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ + uint32_t McEmemArbTimingRas; + /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ + uint32_t McEmemArbTimingFaw; + /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ + uint32_t McEmemArbTimingRrd; + /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ + uint32_t McEmemArbTimingRap2Pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ + uint32_t McEmemArbTimingWap2Pre; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ + uint32_t McEmemArbTimingR2R; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ + uint32_t McEmemArbTimingW2W; + /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ + uint32_t McEmemArbTimingR2W; + /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ + uint32_t McEmemArbTimingW2R; + + uint32_t McEmemArbTimingRFCPB; + + /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ + uint32_t McEmemArbDaTurns; + /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ + uint32_t McEmemArbDaCovers; + /* Specifies the value for MC_EMEM_ARB_MISC0 */ + uint32_t McEmemArbMisc0; + /* Specifies the value for MC_EMEM_ARB_MISC1 */ + uint32_t McEmemArbMisc1; + uint32_t McEmemArbMisc2; + + /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ + uint32_t McEmemArbRing1Throttle; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ + uint32_t McEmemArbOverride; + /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ + uint32_t McEmemArbOverride1; + /* Specifies the value for MC_EMEM_ARB_RSV */ + uint32_t McEmemArbRsv; + + uint32_t McDaCfg0; + uint32_t McEmemArbTimingCcdmw; + + /* Specifies the value for MC_CLKEN_OVERRIDE */ + uint32_t McClkenOverride; + + /* Specifies the value for MC_STAT_CONTROL */ + uint32_t McStatControl; + + /* Specifies the value for MC_VIDEO_PROTECT_BOM */ + uint32_t McVideoProtectBom; + /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ + uint32_t McVideoProtectBomAdrHi; + /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ + uint32_t McVideoProtectSizeMb; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ + uint32_t McVideoProtectVprOverride; + /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ + uint32_t McVideoProtectVprOverride1; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ + uint32_t McVideoProtectGpuOverride0; + /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ + uint32_t McVideoProtectGpuOverride1; + /* Specifies the value for MC_SEC_CARVEOUT_BOM */ + uint32_t McSecCarveoutBom; + /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ + uint32_t McSecCarveoutAdrHi; + /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ + uint32_t McSecCarveoutSizeMb; + /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL. + VIDEO_PROTECT_WRITEAccess */ + uint32_t McVideoProtectWriteAccess; + /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL. + SEC_CARVEOUT_WRITEAccess */ + uint32_t McSecCarveoutProtectWriteAccess; + + /* Write-Protect Regions (WPR) */ + uint32_t McGeneralizedCarveout1Bom; + uint32_t McGeneralizedCarveout1BomHi; + uint32_t McGeneralizedCarveout1Size128kb; + uint32_t McGeneralizedCarveout1Access0; + uint32_t McGeneralizedCarveout1Access1; + uint32_t McGeneralizedCarveout1Access2; + uint32_t McGeneralizedCarveout1Access3; + uint32_t McGeneralizedCarveout1Access4; + uint32_t McGeneralizedCarveout1ForceInternalAccess0; + uint32_t McGeneralizedCarveout1ForceInternalAccess1; + uint32_t McGeneralizedCarveout1ForceInternalAccess2; + uint32_t McGeneralizedCarveout1ForceInternalAccess3; + uint32_t McGeneralizedCarveout1ForceInternalAccess4; + uint32_t McGeneralizedCarveout1Cfg0; + + uint32_t McGeneralizedCarveout2Bom; + uint32_t McGeneralizedCarveout2BomHi; + uint32_t McGeneralizedCarveout2Size128kb; + uint32_t McGeneralizedCarveout2Access0; + uint32_t McGeneralizedCarveout2Access1; + uint32_t McGeneralizedCarveout2Access2; + uint32_t McGeneralizedCarveout2Access3; + uint32_t McGeneralizedCarveout2Access4; + uint32_t McGeneralizedCarveout2ForceInternalAccess0; + uint32_t McGeneralizedCarveout2ForceInternalAccess1; + uint32_t McGeneralizedCarveout2ForceInternalAccess2; + uint32_t McGeneralizedCarveout2ForceInternalAccess3; + uint32_t McGeneralizedCarveout2ForceInternalAccess4; + uint32_t McGeneralizedCarveout2Cfg0; + + uint32_t McGeneralizedCarveout3Bom; + uint32_t McGeneralizedCarveout3BomHi; + uint32_t McGeneralizedCarveout3Size128kb; + uint32_t McGeneralizedCarveout3Access0; + uint32_t McGeneralizedCarveout3Access1; + uint32_t McGeneralizedCarveout3Access2; + uint32_t McGeneralizedCarveout3Access3; + uint32_t McGeneralizedCarveout3Access4; + uint32_t McGeneralizedCarveout3ForceInternalAccess0; + uint32_t McGeneralizedCarveout3ForceInternalAccess1; + uint32_t McGeneralizedCarveout3ForceInternalAccess2; + uint32_t McGeneralizedCarveout3ForceInternalAccess3; + uint32_t McGeneralizedCarveout3ForceInternalAccess4; + uint32_t McGeneralizedCarveout3Cfg0; + + uint32_t McGeneralizedCarveout4Bom; + uint32_t McGeneralizedCarveout4BomHi; + uint32_t McGeneralizedCarveout4Size128kb; + uint32_t McGeneralizedCarveout4Access0; + uint32_t McGeneralizedCarveout4Access1; + uint32_t McGeneralizedCarveout4Access2; + uint32_t McGeneralizedCarveout4Access3; + uint32_t McGeneralizedCarveout4Access4; + uint32_t McGeneralizedCarveout4ForceInternalAccess0; + uint32_t McGeneralizedCarveout4ForceInternalAccess1; + uint32_t McGeneralizedCarveout4ForceInternalAccess2; + uint32_t McGeneralizedCarveout4ForceInternalAccess3; + uint32_t McGeneralizedCarveout4ForceInternalAccess4; + uint32_t McGeneralizedCarveout4Cfg0; + + uint32_t McGeneralizedCarveout5Bom; + uint32_t McGeneralizedCarveout5BomHi; + uint32_t McGeneralizedCarveout5Size128kb; + uint32_t McGeneralizedCarveout5Access0; + uint32_t McGeneralizedCarveout5Access1; + uint32_t McGeneralizedCarveout5Access2; + uint32_t McGeneralizedCarveout5Access3; + uint32_t McGeneralizedCarveout5Access4; + uint32_t McGeneralizedCarveout5ForceInternalAccess0; + uint32_t McGeneralizedCarveout5ForceInternalAccess1; + uint32_t McGeneralizedCarveout5ForceInternalAccess2; + uint32_t McGeneralizedCarveout5ForceInternalAccess3; + uint32_t McGeneralizedCarveout5ForceInternalAccess4; + uint32_t McGeneralizedCarveout5Cfg0; + + /* Specifies enable for CA training */ + uint32_t EmcCaTrainingEnable; + + /* Set if bit 6 select is greater than bit 7 select; uses aremc. + spec packet SWIZZLE_BIT6_GT_BIT7 */ + uint32_t SwizzleRankByteEncode; + /* Specifies enable and offset for patched boot rom write */ + uint32_t BootRomPatchControl; + /* Specifies data for patched boot rom write */ + uint32_t BootRomPatchData; + + /* Specifies the value for MC_MTS_CARVEOUT_BOM */ + uint32_t McMtsCarveoutBom; + /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ + uint32_t McMtsCarveoutAdrHi; + /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ + uint32_t McMtsCarveoutSizeMb; + /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ + uint32_t McMtsCarveoutRegCtrl; + + /* End */ +}; + +check_member(sdram_params, McMtsCarveoutRegCtrl, 0x770); + +#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/secure_boot.h b/src/soc/nvidia/tegra210/include/soc/secure_boot.h new file mode 100644 index 0000000000..306eac782c --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/secure_boot.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA210_SECURE_BOOT_H_ +#define _TEGRA210_SECURE_BOOT_H_ + +struct tegra_secure_boot { + u32 sb_csr; /* offset 0x00 */ + u32 sb_pirom_start; /* offset 0x04 */ + u32 sb_pfcfg; /* offset 0x08 */ + u32 sb_secure_spare_0; /* offset 0x0c */ + u32 sb_secure_spare_1; /* offset 0x10 */ + u32 sb_secure_spare_2; /* offset 0x14 */ + u32 sb_secure_spare_3; /* offset 0x18 */ + u32 sb_secure_spare_4; /* offset 0x1c */ + u32 sb_secure_spare_5; /* offset 0x20 */ + u32 sb_secure_spare_6; /* offset 0x24 */ + u32 sb_secure_spare_7; /* offset 0x28 */ + u32 rsvd; /* offset 0x2c */ + u32 sb_aa64_reset_low; /* offset 0x30 */ + u32 sb_aa64_reset_high; /* offset 0x3c */ +}; + +#endif /* _TEGRA210_SECURE_BOOT_H_ */ diff --git a/src/soc/nvidia/tegra210/include/soc/sor.h b/src/soc/nvidia/tegra210/include/soc/sor.h new file mode 100644 index 0000000000..5d1d6632bb --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/sor.h @@ -0,0 +1,930 @@ +/* + * drivers/video/tegra/dc/sor_regs.h + * + * Copyright (c) 2011-2015, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __TEGRA210_SOR_H__ +#define __TEGRA210_SOR_H__ + +#define NV_SOR_SUPER_STATE0 (0x1) +#define NV_SOR_SUPER_STATE0_UPDATE_SHIFT (0) +#define NV_SOR_SUPER_STATE0_UPDATE_DEFAULT_MASK (0x1) +#define NV_SOR_SUPER_STATE1 (0x2) +#define NV_SOR_SUPER_STATE1_ATTACHED_SHIFT (3) +#define NV_SOR_SUPER_STATE1_ATTACHED_NO (0 << 3) +#define NV_SOR_SUPER_STATE1_ATTACHED_YES (1 << 3) +#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SHIFT (2) +#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE (0 << 2) +#define NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL (1 << 2) +#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SHIFT (0) +#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK (0x3) +#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP (0) +#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SNOOZE (1) +#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE (2) +#define NV_SOR_STATE0 (0x3) +#define NV_SOR_STATE0_UPDATE_SHIFT (0) +#define NV_SOR_STATE0_UPDATE_DEFAULT_MASK (0x1) +#define NV_SOR_STATE1 (0x4) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_SHIFT (17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_DEFAULT_MASK (0xf << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_16_422 (1 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444 (2 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_20_422 (3 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_422 (4 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 (5 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_30_444 (6 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_32_422 (7 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_36_444 (8 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_48_444 (9 << 17) +#define NV_SOR_STATE1_ASY_REPLICATE_SHIFT (15) +#define NV_SOR_STATE1_ASY_REPLICATE_DEFAULT_MASK (0x3 << 15) +#define NV_SOR_STATE1_ASY_REPLICATE_OFF (0 << 15) +#define NV_SOR_STATE1_ASY_REPLICATE_X2 (1 << 15) +#define NV_SOR_STATE1_ASY_REPLICATE_X4 (2 << 15) +#define NV_SOR_STATE1_ASY_DEPOL_SHIFT (14) +#define NV_SOR_STATE1_ASY_DEPOL_DEFAULT_MASK (0x1 << 14) +#define NV_SOR_STATE1_ASY_DEPOL_POSITIVE_TRUE (0 << 14) +#define NV_SOR_STATE1_ASY_DEPOL_NEGATIVE_TRUE (1 << 14) +#define NV_SOR_STATE1_ASY_VSYNCPOL_SHIFT (13) +#define NV_SOR_STATE1_ASY_VSYNCPOL_DEFAULT_MASK (0x1 << 13) +#define NV_SOR_STATE1_ASY_VSYNCPOL_POSITIVE_TRUE (0 << 13) +#define NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (1 << 13) +#define NV_SOR_STATE1_ASY_HSYNCPOL_SHIFT (12) +#define NV_SOR_STATE1_ASY_HSYNCPOL_DEFAULT_MASK (0x1 << 12) +#define NV_SOR_STATE1_ASY_HSYNCPOL_POSITIVE_TRUE (0 << 12) +#define NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE (1 << 12) +#define NV_SOR_STATE1_ASY_PROTOCOL_SHIFT (8) +#define NV_SOR_STATE1_ASY_PROTOCOL_DEFAULT_MASK (0xf << 8) +#define NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM (0 << 8) +#define NV_SOR_STATE1_ASY_PROTOCOL_DP_A (8 << 8) +#define NV_SOR_STATE1_ASY_PROTOCOL_DP_B (9 << 8) +#define NV_SOR_STATE1_ASY_PROTOCOL_CUSTOM (15 << 8) +#define NV_SOR_STATE1_ASY_CRCMODE_SHIFT (6) +#define NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK (0x3 << 6) +#define NV_SOR_STATE1_ASY_CRCMODE_ACTIVE_RASTER (0 << 6) +#define NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER (1 << 6) +#define NV_SOR_STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER (2 << 6) +#define NV_SOR_STATE1_ASY_SUBOWNER_SHIFT (4) +#define NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK (0x3 << 4) +#define NV_SOR_STATE1_ASY_SUBOWNER_NONE (0 << 4) +#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD0 (1 << 4) +#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD1 (2 << 4) +#define NV_SOR_STATE1_ASY_SUBOWNER_BOTH (3 << 4) +#define NV_SOR_STATE1_ASY_OWNER_SHIFT (0) +#define NV_SOR_STATE1_ASY_OWNER_DEFAULT_MASK (0xf) +#define NV_SOR_STATE1_ASY_OWNER_NONE (0) +#define NV_SOR_STATE1_ASY_OWNER_HEAD0 (1) +#define NV_SOR_STATE1_ASY_OWNER_HEAD1 (2) +#define NV_HEAD_STATE0(i) (0x5) +#define NV_HEAD_STATE0_INTERLACED_SHIFT (4) +#define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK (0x3 << 4) +#define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE (0 << 4) +#define NV_HEAD_STATE0_INTERLACED_INTERLACED (1 << 4) +#define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT (3) +#define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK (0x1 << 3) +#define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE (0 << 3) +#define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE (1 << 3) +#define NV_HEAD_STATE0_DYNRANGE_SHIFT (2) +#define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK (0x1 << 2) +#define NV_HEAD_STATE0_DYNRANGE_VESA (0 << 2) +#define NV_HEAD_STATE0_DYNRANGE_CEA (1 << 2) +#define NV_HEAD_STATE0_COLORSPACE_SHIFT (0) +#define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK (0x3) +#define NV_HEAD_STATE0_COLORSPACE_RGB (0) +#define NV_HEAD_STATE0_COLORSPACE_YUV_601 (1) +#define NV_HEAD_STATE0_COLORSPACE_YUV_709 (2) +#define NV_HEAD_STATE1(i) (0x7 + i) +#define NV_HEAD_STATE1_VTOTAL_SHIFT (16) +#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE1_HTOTAL_SHIFT (0) +#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK (0x7fff) +#define NV_HEAD_STATE2(i) (0x9 + i) +#define NV_HEAD_STATE2_VSYNC_END_SHIFT (16) +#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE2_HSYNC_END_SHIFT (0) +#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK (0x7fff) +#define NV_HEAD_STATE3(i) (0xb + i) +#define NV_HEAD_STATE3_VBLANK_END_SHIFT (16) +#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE3_HBLANK_END_SHIFT (0) +#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK (0x7fff) +#define NV_HEAD_STATE4(i) (0xd + i) +#define NV_HEAD_STATE4_VBLANK_START_SHIFT (16) +#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE4_HBLANK_START_SHIFT (0) +#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK (0x7fff) +#define NV_HEAD_STATE5(i) (0xf + i) +#define NV_SOR_CRC_CNTRL (0x11) +#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_SHIFT (0) +#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_NO (0) +#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_YES (1) +#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DIS (0) +#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_EN (1) +#define NV_SOR_CLK_CNTRL (0x13) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SHIFT (0) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK (0x3) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK (0) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK (1) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK (2) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK (3) +#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT (2) +#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2) +#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62 (6 << 2) +#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7 (10 << 2) +#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS (7 << 2) +#define NV_SOR_CAP (0x14) +#define NV_SOR_CAP_DP_A_SHIFT (24) +#define NV_SOR_CAP_DP_A_DEFAULT_MASK (0x1 << 24) +#define NV_SOR_CAP_DP_A_FALSE (0 << 24) +#define NV_SOR_CAP_DP_A_TRUE (1 << 24) +#define NV_SOR_CAP_DP_B_SHIFT (25) +#define NV_SOR_CAP_DP_B_DEFAULT_MASK (0x1 << 24) +#define NV_SOR_CAP_DP_B_FALSE (0 << 24) +#define NV_SOR_CAP_DP_B_TRUE (1 << 24) +#define NV_SOR_PWR (0x15) +#define NV_SOR_PWR_SETTING_NEW_SHIFT (31) +#define NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK (0x1 << 31) +#define NV_SOR_PWR_SETTING_NEW_DONE (0 << 31) +#define NV_SOR_PWR_SETTING_NEW_PENDING (1 << 31) +#define NV_SOR_PWR_SETTING_NEW_TRIGGER (1 << 31) +#define NV_SOR_PWR_MODE_SHIFT (28) +#define NV_SOR_PWR_MODE_DEFAULT_MASK (0x1 << 28) +#define NV_SOR_PWR_MODE_NORMAL (0 << 28) +#define NV_SOR_PWR_MODE_SAFE (1 << 28) +#define NV_SOR_PWR_HALT_DELAY_SHIFT (24) +#define NV_SOR_PWR_HALT_DELAY_DEFAULT_MASK (0x1 << 24) +#define NV_SOR_PWR_HALT_DELAY_DONE (0 << 24) +#define NV_SOR_PWR_HALT_DELAY_ACTIVE (1 << 24) +#define NV_SOR_PWR_SAFE_START_SHIFT (17) +#define NV_SOR_PWR_SAFE_START_DEFAULT_MASK (0x1 << 17) +#define NV_SOR_PWR_SAFE_START_NORMAL (0 << 17) +#define NV_SOR_PWR_SAFE_START_ALT (1 << 17) +#define NV_SOR_PWR_SAFE_STATE_SHIFT (16) +#define NV_SOR_PWR_SAFE_STATE_DEFAULT_MASK (0x1 << 16) +#define NV_SOR_PWR_SAFE_STATE_PD (0 << 16) +#define NV_SOR_PWR_SAFE_STATE_PU (1 << 16) +#define NV_SOR_PWR_NORMAL_START_SHIFT (1) +#define NV_SOR_PWR_NORMAL_START_DEFAULT_MASK (0x1 << 1) +#define NV_SOR_PWR_NORMAL_START_NORMAL (0 << 16) +#define NV_SOR_PWR_NORMAL_START_ALT (1 << 16) +#define NV_SOR_PWR_NORMAL_STATE_SHIFT (0) +#define NV_SOR_PWR_NORMAL_STATE_DEFAULT_MASK (0x1) +#define NV_SOR_PWR_NORMAL_STATE_PD (0) +#define NV_SOR_PWR_NORMAL_STATE_PU (1) +#define NV_SOR_TEST (0x16) +#define NV_SOR_TEST_TESTMUX_SHIFT (24) +#define NV_SOR_TEST_TESTMUX_DEFAULT_MASK (0xff << 24) +#define NV_SOR_TEST_TESTMUX_AVSS (0 << 24) +#define NV_SOR_TEST_TESTMUX_CLOCKIN (2 << 24) +#define NV_SOR_TEST_TESTMUX_PLL_VOL (4 << 24) +#define NV_SOR_TEST_TESTMUX_SLOWCLKINT (8 << 24) +#define NV_SOR_TEST_TESTMUX_AVDD (16 << 24) +#define NV_SOR_TEST_TESTMUX_VDDREG (32 << 24) +#define NV_SOR_TEST_TESTMUX_REGREF_VDDREG (64 << 24) +#define NV_SOR_TEST_TESTMUX_REGREF_AVDD (128 << 24) +#define NV_SOR_TEST_CRC_SHIFT (23) +#define NV_SOR_TEST_CRC_PRE_SERIALIZE (0 << 23) +#define NV_SOR_TEST_CRC_POST_DESERIALIZE (1 << 23) +#define NV_SOR_TEST_TPAT_SHIFT (20) +#define NV_SOR_TEST_TPAT_DEFAULT_MASK (0x7 << 20) +#define NV_SOR_TEST_TPAT_LO (0 << 20) +#define NV_SOR_TEST_TPAT_TDAT (1 << 20) +#define NV_SOR_TEST_TPAT_RAMP (2 << 20) +#define NV_SOR_TEST_TPAT_WALK (3 << 20) +#define NV_SOR_TEST_TPAT_MAXSTEP (4 << 20) +#define NV_SOR_TEST_TPAT_MINSTEP (5 << 20) +#define NV_SOR_TEST_DSRC_SHIFT (16) +#define NV_SOR_TEST_DSRC_DEFAULT_MASK (0x3 << 16) +#define NV_SOR_TEST_DSRC_NORMAL (0 << 16) +#define NV_SOR_TEST_DSRC_DEBUG (1 << 16) +#define NV_SOR_TEST_DSRC_TGEN (2 << 16) +#define NV_SOR_TEST_HEAD_NUMBER_SHIFT (12) +#define NV_SOR_TEST_HEAD_NUMBER_DEFAULT_MASK (0x3 << 12) +#define NV_SOR_TEST_HEAD_NUMBER_NONE (0 << 12) +#define NV_SOR_TEST_HEAD_NUMBER_HEAD0 (1 << 12) +#define NV_SOR_TEST_HEAD_NUMBER_HEAD1 (2 << 12) +#define NV_SOR_TEST_ATTACHED_SHIFT (10) +#define NV_SOR_TEST_ATTACHED_DEFAULT_MASK (0x1 << 10) +#define NV_SOR_TEST_ATTACHED_FALSE (0 << 10) +#define NV_SOR_TEST_ATTACHED_TRUE (1 << 10) +#define NV_SOR_TEST_ACT_HEAD_OPMODE_SHIFT (8) +#define NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK (0x3 << 8) +#define NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP (0 << 8) +#define NV_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE (1 << 8) +#define NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE (2 << 8) +#define NV_SOR_TEST_INVD_SHIFT (6) +#define NV_SOR_TEST_INVD_DISABLE (0 << 6) +#define NV_SOR_TEST_INVD_ENABLE (1 << 6) +#define NV_SOR_TEST_TEST_ENABLE_SHIFT (1) +#define NV_SOR_TEST_TEST_ENABLE_DISABLE (0 << 1) +#define NV_SOR_TEST_TEST_ENABLE_ENABLE (1 << 1) +#define NV_SOR_PLL0 (0x17) +#define NV_SOR_PLL0_ICHPMP_SHFIT (24) +#define NV_SOR_PLL0_ICHPMP_DEFAULT_MASK (0xf << 24) +#define NV_SOR_PLL0_VCOCAP_SHIFT (8) +#define NV_SOR_PLL0_VCOCAP_DEFAULT_MASK (0xf << 8) +#define NV_SOR_PLL0_PLLREG_LEVEL_SHIFT (6) +#define NV_SOR_PLL0_PLLREG_LEVEL_DEFAULT_MASK (0x3 << 6) +#define NV_SOR_PLL0_PLLREG_LEVEL_V25 (0 << 6) +#define NV_SOR_PLL0_PLLREG_LEVEL_V15 (1 << 6) +#define NV_SOR_PLL0_PLLREG_LEVEL_V35 (2 << 6) +#define NV_SOR_PLL0_PLLREG_LEVEL_V45 (3 << 6) +#define NV_SOR_PLL0_PULLDOWN_SHIFT (5) +#define NV_SOR_PLL0_PULLDOWN_DEFAULT_MASK (0x1 << 5) +#define NV_SOR_PLL0_PULLDOWN_DISABLE (0 << 5) +#define NV_SOR_PLL0_PULLDOWN_ENABLE (1 << 5) +#define NV_SOR_PLL0_RESISTORSEL_SHIFT (4) +#define NV_SOR_PLL0_RESISTORSEL_DEFAULT_MASK (0x1 << 4) +#define NV_SOR_PLL0_RESISTORSEL_INT (0 << 4) +#define NV_SOR_PLL0_RESISTORSEL_EXT (1 << 4) +#define NV_SOR_PLL0_VCOPD_SHIFT (2) +#define NV_SOR_PLL0_VCOPD_MASK (1 << 2) +#define NV_SOR_PLL0_VCOPD_RESCIND (0 << 2) +#define NV_SOR_PLL0_VCOPD_ASSERT (1 << 2) +#define NV_SOR_PLL0_PWR_SHIFT (0) +#define NV_SOR_PLL0_PWR_MASK (1) +#define NV_SOR_PLL0_PWR_ON (0) +#define NV_SOR_PLL0_PWR_OFF (1) +#define NV_SOR_PLL1_TMDS_TERM_SHIFT (8) +#define NV_SOR_PLL1_TMDS_TERM_DISABLE (0 << 8) +#define NV_SOR_PLL1_TMDS_TERM_ENABLE (1 << 8) +#define NV_SOR_PLL1 (0x18) +#define NV_SOR_PLL1_TERM_COMPOUT_SHIFT (15) +#define NV_SOR_PLL1_TERM_COMPOUT_LOW (0 << 15) +#define NV_SOR_PLL1_TERM_COMPOUT_HIGH (1 << 15) +#define NV_SOR_PLL2 (0x19) +#define NV_SOR_PLL2_DCIR_PLL_RESET_SHIFT (0) +#define NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE (0 << 0) +#define NV_SOR_PLL2_DCIR_PLL_RESET_ALLOW (1 << 0) +#define NV_SOR_PLL2_AUX1_SHIFT (17) +#define NV_SOR_PLL2_AUX1_SEQ_MASK (1 << 17) +#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_ALLOW (0 << 17) +#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE (1 << 17) +#define NV_SOR_PLL2_AUX2_SHIFT (18) +#define NV_SOR_PLL2_AUX2_MASK (1 << 18) +#define NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN (0 << 18) +#define NV_SOR_PLL2_AUX2_ALLOW_POWERDOWN (1 << 18) +#define NV_SOR_PLL2_AUX6_SHIFT (22) +#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK (1 << 22) +#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE (0 << 22) +#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE (1 << 22) +#define NV_SOR_PLL2_AUX7_SHIFT (23) +#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK (1 << 23) +#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE (0 << 23) +#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE (1 << 23) +#define NV_SOR_PLL2_AUX8_SHIFT (24) +#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK (1 << 24) +#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24) +#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24) +#define NV_SOR_PLL2_AUX9_SHIFT (25) +#define NV_SOR_PLL2_AUX9_LVDSEN_ALLOW (0 << 25) +#define NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE (1 << 25) +#define NV_SOR_PLL3 (0x1a) +#define NV_SOR_PLL3_PLLVDD_MODE_SHIFT (13) +#define NV_SOR_PLL3_PLLVDD_MODE_MASK (1 << 13) +#define NV_SOR_PLL3_PLLVDD_MODE_V1_8 (0 << 13) +#define NV_SOR_PLL3_PLLVDD_MODE_V3_3 (1 << 13) +#define NV_SOR_CSTM (0x1b) +#define NV_SOR_CSTM_ROTDAT_SHIFT (28) +#define NV_SOR_CSTM_ROTDAT_DEFAULT_MASK (0x7 << 28) +#define NV_SOR_CSTM_ROTCLK_SHIFT (24) +#define NV_SOR_CSTM_ROTCLK_DEFAULT_MASK (0xf << 24) +#define NV_SOR_CSTM_LVDS_EN_SHIFT (16) +#define NV_SOR_CSTM_LVDS_EN_DISABLE (0 << 16) +#define NV_SOR_CSTM_LVDS_EN_ENABLE (1 << 16) +#define NV_SOR_CSTM_LINKACTB_SHIFT (15) +#define NV_SOR_CSTM_LINKACTB_DISABLE (0 << 15) +#define NV_SOR_CSTM_LINKACTB_ENABLE (1 << 15) +#define NV_SOR_CSTM_LINKACTA_SHIFT (14) +#define NV_SOR_CSTM_LINKACTA_DISABLE (0 << 14) +#define NV_SOR_CSTM_LINKACTA_ENABLE (1 << 14) +#define NV_SOR_LVDS (0x1c) +#define NV_SOR_LVDS_ROTDAT_SHIFT (28) +#define NV_SOR_LVDS_ROTDAT_DEFAULT_MASK (0x7 << 28) +#define NV_SOR_LVDS_ROTDAT_RST (0 << 28) +#define NV_SOR_LVDS_ROTCLK_SHIFT (24) +#define NV_SOR_LVDS_ROTCLK_DEFAULT_MASK (0xf << 24) +#define NV_SOR_LVDS_ROTCLK_RST (0 << 24) +#define NV_SOR_LVDS_PLLDIV_SHIFT (21) +#define NV_SOR_LVDS_PLLDIV_DEFAULT_MASK (0x1 << 21) +#define NV_SOR_LVDS_PLLDIV_BY_7 (0 << 21) +#define NV_SOR_LVDS_BALANCED_SHIFT (19) +#define NV_SOR_LVDS_BALANCED_DEFAULT_MASK (0x1 << 19) +#define NV_SOR_LVDS_BALANCED_DISABLE (0 << 19) +#define NV_SOR_LVDS_BALANCED_ENABLE (1 << 19) +#define NV_SOR_LVDS_NEW_MODE_SHIFT (18) +#define NV_SOR_LVDS_NEW_MODE_DEFAULT_MASK (0x1 << 18) +#define NV_SOR_LVDS_NEW_MODE_DISABLE (0 << 18) +#define NV_SOR_LVDS_NEW_MODE_ENABLE (1 << 18) +#define NV_SOR_LVDS_DUP_SYNC_SHIFT (17) +#define NV_SOR_LVDS_DUP_SYNC_DEFAULT_MASK (0x1 << 17) +#define NV_SOR_LVDS_DUP_SYNC_DISABLE (0 << 17) +#define NV_SOR_LVDS_DUP_SYNC_ENABLE (1 << 17) +#define NV_SOR_LVDS_LVDS_EN_SHIFT (16) +#define NV_SOR_LVDS_LVDS_EN_DEFAULT_MASK (0x1 << 16) +#define NV_SOR_LVDS_LVDS_EN_ENABLE (1 << 16) +#define NV_SOR_LVDS_LINKACTB_SHIFT (15) +#define NV_SOR_LVDS_LINKACTB_DEFAULT_MASK (0x1 << 15) +#define NV_SOR_LVDS_LINKACTB_DISABLE (0 << 15) +#define NV_SOR_LVDS_LINKACTB_ENABLE (1 << 15) +#define NV_SOR_LVDS_LINKACTA_SHIFT (14) +#define NV_SOR_LVDS_LINKACTA_DEFAULT_MASK (0x1 << 14) +#define NV_SOR_LVDS_LINKACTA_ENABLE (1 << 14) +#define NV_SOR_LVDS_MODE_SHIFT (12) +#define NV_SOR_LVDS_MODE_DEFAULT_MASK (0x3 << 12) +#define NV_SOR_LVDS_MODE_LVDS (0 << 12) +#define NV_SOR_LVDS_UPPER_SHIFT (11) +#define NV_SOR_LVDS_UPPER_DEFAULT_MASK (0x1 << 11) +#define NV_SOR_LVDS_UPPER_FALSE (0 << 11) +#define NV_SOR_LVDS_UPPER_TRUE (1 << 11) +#define NV_SOR_LVDS_PD_TXCB_SHIFT (9) +#define NV_SOR_LVDS_PD_TXCB_DEFAULT_MASK (0x1 << 9) +#define NV_SOR_LVDS_PD_TXCB_ENABLE (0 << 9) +#define NV_SOR_LVDS_PD_TXCB_DISABLE (1 << 9) +#define NV_SOR_LVDS_PD_TXCA_SHIFT (8) +#define NV_SOR_LVDS_PD_TXCA_DEFAULT_MASK (0x1 << 8) +#define NV_SOR_LVDS_PD_TXCA_ENABLE (0 << 8) +#define NV_SOR_LVDS_PD_TXDB_3_SHIFT (7) +#define NV_SOR_LVDS_PD_TXDB_3_DEFAULT_MASK (0x1 << 7) +#define NV_SOR_LVDS_PD_TXDB_3_ENABLE (0 << 7) +#define NV_SOR_LVDS_PD_TXDB_3_DISABLE (1 << 7) +#define NV_SOR_LVDS_PD_TXDB_2_SHIFT (6) +#define NV_SOR_LVDS_PD_TXDB_2_DEFAULT_MASK (0x1 << 6) +#define NV_SOR_LVDS_PD_TXDB_2_ENABLE (0 << 6) +#define NV_SOR_LVDS_PD_TXDB_2_DISABLE (1 << 6) +#define NV_SOR_LVDS_PD_TXDB_1_SHIFT (5) +#define NV_SOR_LVDS_PD_TXDB_1_DEFAULT_MASK (0x1 << 5) +#define NV_SOR_LVDS_PD_TXDB_1_ENABLE (0 << 5) +#define NV_SOR_LVDS_PD_TXDB_1_DISABLE (1 << 5) +#define NV_SOR_LVDS_PD_TXDB_0_SHIFT (4) +#define NV_SOR_LVDS_PD_TXDB_0_DEFAULT_MASK (0x1 << 4) +#define NV_SOR_LVDS_PD_TXDB_0_ENABLE (0 << 4) +#define NV_SOR_LVDS_PD_TXDB_0_DISABLE (1 << 4) +#define NV_SOR_LVDS_PD_TXDA_3_SHIFT (3) +#define NV_SOR_LVDS_PD_TXDA_3_DEFAULT_MASK (0x1 << 3) +#define NV_SOR_LVDS_PD_TXDA_3_ENABLE (0 << 3) +#define NV_SOR_LVDS_PD_TXDA_3_DISABLE (1 << 3) +#define NV_SOR_LVDS_PD_TXDA_2_SHIFT (2) +#define NV_SOR_LVDS_PD_TXDA_2_DEFAULT_MASK (0x1 << 2) +#define NV_SOR_LVDS_PD_TXDA_2_ENABLE (0 << 2) +#define NV_SOR_LVDS_PD_TXDA_1_SHIFT (1) +#define NV_SOR_LVDS_PD_TXDA_1_DEFAULT_MASK (0x1 << 1) +#define NV_SOR_LVDS_PD_TXDA_1_ENABLE (0 << 1) +#define NV_SOR_LVDS_PD_TXDA_0_SHIFT (0) +#define NV_SOR_LVDS_PD_TXDA_0_DEFAULT_MASK (0x1) +#define NV_SOR_LVDS_PD_TXDA_0_ENABLE (0) +#define NV_SOR_CRCA (0x1d) +#define NV_SOR_CRCA_VALID_FALSE (0) +#define NV_SOR_CRCA_VALID_TRUE (1) +#define NV_SOR_CRCA_VALID_RST (1) +#define NV_SOR_CRCB (0x1e) +#define NV_SOR_CRCB_CRC_DEFAULT_MASK (0xffffffff) +#define NV_SOR_SEQ_CTL (0x20) +#define NV_SOR_SEQ_CTL_SWITCH_SHIFT (30) +#define NV_SOR_SEQ_CTL_SWITCH_MASK (0x1 << 30) +#define NV_SOR_SEQ_CTL_SWITCH_WAIT (0 << 30) +#define NV_SOR_SEQ_CTL_SWITCH_FORCE (1 << 30) +#define NV_SOR_SEQ_CTL_STATUS_SHIFT (28) +#define NV_SOR_SEQ_CTL_STATUS_MASK (0x1 << 28) +#define NV_SOR_SEQ_CTL_STATUS_STOPPED (0 << 28) +#define NV_SOR_SEQ_CTL_STATUS_RUNNING (1 << 28) +#define NV_SOR_SEQ_CTL_PC_SHIFT (16) +#define NV_SOR_SEQ_CTL_PC_MASK (0xf << 16) +#define NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT (12) +#define NV_SOR_SEQ_CTL_PD_PC_ALT_MASK (0xf << 12) +#define NV_SOR_SEQ_CTL_PD_PC_SHIFT (8) +#define NV_SOR_SEQ_CTL_PD_PC_MASK (0xf << 8) +#define NV_SOR_SEQ_CTL_PU_PC_ALT_SHIFT (4) +#define NV_SOR_SEQ_CTL_PU_PC_ALT_MASK (0xf << 4) +#define NV_SOR_SEQ_CTL_PU_PC_SHIFT (0) +#define NV_SOR_SEQ_CTL_PU_PC_MASK (0xf) +#define NV_SOR_LANE_SEQ_CTL (0x21) +#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_SHIFT (31) +#define NV_SOR_LANE_SEQ_CTL_SETTING_MASK (1 << 31) +#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE (0 << 31) +#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_PENDING (1 << 31) +#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER (1 << 31) +#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_SHIFT (28) +#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE (0 << 28) +#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY (1 << 28) +#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_SHIFT (20) +#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP (0 << 20) +#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20) +#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT (16) +#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU (0 << 16) +#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD (1 << 16) +#define NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT (12) +#define NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK (0xf << 12) +#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_SHIFT (9) +#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERUP (0 << 9) +#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERDOWN (1 << 9) +#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_SHIFT (8) +#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERUP (0 << 8) +#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERDOWN (1 << 8) +#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_SHIFT (7) +#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERUP (0 << 7) +#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERDOWN (1 << 7) +#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_SHIFT (6) +#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERUP (0 << 6) +#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERDOWN (1 << 6) +#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_SHIFT (5) +#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERUP (0 << 5) +#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERDOWN (1 << 5) +#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_SHIFT (4) +#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERUP (0 << 4) +#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERDOWN (1 << 4) +#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_SHIFT (3) +#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERUP (0 << 3) +#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERDOWN (1 << 3) +#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_SHIFT (2) +#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERUP (0 << 2) +#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERDOWN (1 << 2) +#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_SHIFT (1) +#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERUP (0 << 1) +#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERDOWN (1 << 1) +#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_SHIFT (0) +#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERUP (0) +#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERDOWN (1) +#define NV_SOR_SEQ_INST(i) (0x22 + i) +#define NV_SOR_SEQ_INST_PLL_PULLDOWN_SHIFT (31) +#define NV_SOR_SEQ_INST_PLL_PULLDOWN_DISABLE (0 << 31) +#define NV_SOR_SEQ_INST_PLL_PULLDOWN_ENABLE (1 << 31) +#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_SHIFT (30) +#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL (0 << 30) +#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_POWERDOWN (1 << 30) +#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_SHIFT (29) +#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_NORMAL (0 << 29) +#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_RST (1 << 29) +#define NV_SOR_SEQ_INST_BLANK_V_SHIFT (28) +#define NV_SOR_SEQ_INST_BLANK_V_NORMAL (0 << 28) +#define NV_SOR_SEQ_INST_BLANK_V_INACTIVE (1 << 28) +#define NV_SOR_SEQ_INST_BLANK_H_SHIFT (27) +#define NV_SOR_SEQ_INST_BLANK_H_NORMAL (0 << 27) +#define NV_SOR_SEQ_INST_BLANK_H_INACTIVE (1 << 27) +#define NV_SOR_SEQ_INST_BLANK_DE_SHIFT (26) +#define NV_SOR_SEQ_INST_BLANK_DE_NORMAL (0 << 26) +#define NV_SOR_SEQ_INST_BLANK_DE_INACTIVE (1 << 26) +#define NV_SOR_SEQ_INST_BLACK_DATA_SHIFT (25) +#define NV_SOR_SEQ_INST_BLACK_DATA_NORMAL (0 << 25) +#define NV_SOR_SEQ_INST_BLACK_DATA_BLACK (1 << 25) +#define NV_SOR_SEQ_INST_TRISTATE_IOS_SHIFT (24) +#define NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS (0 << 24) +#define NV_SOR_SEQ_INST_TRISTATE_IOS_TRISTATE (1 << 24) +#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT (23) +#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_FALSE (0 << 23) +#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE (1 << 23) +#define NV_SOR_SEQ_INST_PIN_B_SHIFT (22) +#define NV_SOR_SEQ_INST_PIN_B_LOW (0 << 22) +#define NV_SOR_SEQ_INST_PIN_B_HIGH (1 << 22) +#define NV_SOR_SEQ_INST_PIN_A_SHIFT (21) +#define NV_SOR_SEQ_INST_PIN_A_LOW (0 << 21) +#define NV_SOR_SEQ_INST_PIN_A_HIGH (1 << 21) +#define NV_SOR_SEQ_INST_SEQUENCE_SHIFT (19) +#define NV_SOR_SEQ_INST_SEQUENCE_UP (0 << 19) +#define NV_SOR_SEQ_INST_SEQUENCE_DOWN (1 << 19) +#define NV_SOR_SEQ_INST_LANE_SEQ_SHIFT (18) +#define NV_SOR_SEQ_INST_LANE_SEQ_STOP (0 << 18) +#define NV_SOR_SEQ_INST_LANE_SEQ_RUN (1 << 18) +#define NV_SOR_SEQ_INST_PDPORT_SHIFT (17) +#define NV_SOR_SEQ_INST_PDPORT_NO (0 << 17) +#define NV_SOR_SEQ_INST_PDPORT_YES (1 << 17) +#define NV_SOR_SEQ_INST_PDPLL_SHIFT (16) +#define NV_SOR_SEQ_INST_PDPLL_NO (0 << 16) +#define NV_SOR_SEQ_INST_PDPLL_YES (1 << 16) +#define NV_SOR_SEQ_INST_HALT_SHIFT (15) +#define NV_SOR_SEQ_INST_HALT_FALSE (0 << 15) +#define NV_SOR_SEQ_INST_HALT_TRUE (1 << 15) +#define NV_SOR_SEQ_INST_WAIT_UNITS_SHIFT (12) +#define NV_SOR_SEQ_INST_WAIT_UNITS_DEFAULT_MASK (0x3 << 12) +#define NV_SOR_SEQ_INST_WAIT_UNITS_US (0 << 12) +#define NV_SOR_SEQ_INST_WAIT_UNITS_MS (1 << 12) +#define NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12) +#define NV_SOR_SEQ_INST_WAIT_TIME_SHIFT (0) +#define NV_SOR_SEQ_INST_WAIT_TIME_DEFAULT_MASK (0x3ff) +#define NV_SOR_PWM_DIV (0x32) +#define NV_SOR_PWM_DIV_DIVIDE_DEFAULT_MASK (0xffffff) +#define NV_SOR_PWM_CTL (0x33) +#define NV_SOR_PWM_CTL_SETTING_NEW_SHIFT (31) +#define NV_SOR_PWM_CTL_SETTING_NEW_DONE (0 << 31) +#define NV_SOR_PWM_CTL_SETTING_NEW_PENDING (1 << 31) +#define NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER (1 << 31) +#define NV_SOR_PWM_CTL_CLKSEL_SHIFT (30) +#define NV_SOR_PWM_CTL_CLKSEL_PCLK (0 << 30) +#define NV_SOR_PWM_CTL_CLKSEL_XTAL (1 << 30) +#define NV_SOR_PWM_CTL_DUTY_CYCLE_SHIFT (0) +#define NV_SOR_PWM_CTL_DUTY_CYCLE_MASK (0xffffff) +#define NV_SOR_MSCHECK (0x49) +#define NV_SOR_MSCHECK_CTL_SHIFT (31) +#define NV_SOR_MSCHECK_CTL_CLEAR (0 << 31) +#define NV_SOR_MSCHECK_CTL_RUN (1 << 31) +#define NV_SOR_XBAR_CTRL (0x4a) +#define NV_SOR_DP_LINKCTL(i) (0x4c + (i)) +#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT (31) +#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO (0 << 31) +#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES (1 << 31) +#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_SHIFT (28) +#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN (0 << 28) +#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE (1 << 28) +#define NV_SOR_DP_LINKCTL_LANECOUNT_SHIFT (16) +#define NV_SOR_DP_LINKCTL_LANECOUNT_MASK (0x1f << 16) +#define NV_SOR_DP_LINKCTL_LANECOUNT_ZERO (0 << 16) +#define NV_SOR_DP_LINKCTL_LANECOUNT_ONE (1 << 16) +#define NV_SOR_DP_LINKCTL_LANECOUNT_TWO (3 << 16) +#define NV_SOR_DP_LINKCTL_LANECOUNT_FOUR (15 << 16) +#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_SHIFT (14) +#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE (0 << 14) +#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE (1 << 14) +#define NV_SOR_DP_LINKCTL_SYNCMODE_SHIFT (10) +#define NV_SOR_DP_LINKCTL_SYNCMODE_DISABLE (0 << 10) +#define NV_SOR_DP_LINKCTL_SYNCMODE_ENABLE (1 << 10) +#define NV_SOR_DP_LINKCTL_TUSIZE_SHIFT (2) +#define NV_SOR_DP_LINKCTL_TUSIZE_MASK (0x7f << 2) +#define NV_SOR_DP_LINKCTL_ENABLE_SHIFT (0) +#define NV_SOR_DP_LINKCTL_ENABLE_NO (0) +#define NV_SOR_DP_LINKCTL_ENABLE_YES (1) +#define NV_SOR_DC(i) (0x4e + (i)) +#define NV_SOR_DC_LANE3_DP_LANE3_SHIFT (24) +#define NV_SOR_DC_LANE3_DP_LANE3_MASK (0xff << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL0 (17 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0 (21 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL0 (26 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P3_LEVEL0 (34 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL1 (26 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL1 (32 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL1 (39 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL2 (34 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL2 (43 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL3 (51 << 24) +#define NV_SOR_DC_LANE2_DP_LANE0_SHIFT (16) +#define NV_SOR_DC_LANE2_DP_LANE0_MASK (0xff << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL0 (17 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0 (21 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL0 (26 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P3_LEVEL0 (34 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL1 (26 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL1 (32 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL1 (39 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL2 (34 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL2 (43 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL3 (51 << 16) +#define NV_SOR_DC_LANE1_DP_LANE1_SHIFT (8) +#define NV_SOR_DC_LANE1_DP_LANE1_MASK (0xff << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL0 (17 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0 (21 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL0 (26 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P3_LEVEL0 (34 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL1 (26 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL1 (32 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL1 (39 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL2 (34 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL2 (43 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL3 (51 << 8) +#define NV_SOR_DC_LANE0_DP_LANE2_SHIFT (0) +#define NV_SOR_DC_LANE0_DP_LANE2_MASK (0xff) +#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL0 (17) +#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0 (21) +#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL0 (26) +#define NV_SOR_DC_LANE0_DP_LANE2_P3_LEVEL0 (34) +#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL1 (26) +#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL1 (32) +#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL1 (39) +#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL2 (34) +#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2 (43) +#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3 (51) +#define NV_SOR_LANE_DRIVE_CURRENT(i) (0x4e + (i)) +#define NV_SOR_PR(i) (0x52 + (i)) +#define NV_SOR_PR_LANE3_DP_LANE3_SHIFT (24) +#define NV_SOR_PR_LANE3_DP_LANE3_MASK (0xff << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL0 (0 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL0 (0 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL0 (0 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D3_LEVEL0 (0 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL1 (4 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL1 (6 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL1 (17 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL2 (8 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL2 (13 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL3 (17 << 24) +#define NV_SOR_PR_LANE2_DP_LANE0_SHIFT (16) +#define NV_SOR_PR_LANE2_DP_LANE0_MASK (0xff << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL0 (0 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL0 (0 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL0 (0 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D3_LEVEL0 (0 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL1 (4 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL1 (6 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL1 (17 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL2 (8 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL2 (13 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL3 (17 << 16) +#define NV_SOR_PR_LANE1_DP_LANE1_SHIFT (8) +#define NV_SOR_PR_LANE1_DP_LANE1_MASK (0xff >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL0 (0 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL0 (0 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL0 (0 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D3_LEVEL0 (0 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL1 (4 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL1 (6 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL1 (17 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL2 (8 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL2 (13 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL3 (17 >> 8) +#define NV_SOR_PR_LANE0_DP_LANE2_SHIFT (0) +#define NV_SOR_PR_LANE0_DP_LANE2_MASK (0xff) +#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL0 (0) +#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL0 (0) +#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL0 (0) +#define NV_SOR_PR_LANE0_DP_LANE2_D3_LEVEL0 (0) +#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL1 (4) +#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL1 (6) +#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL1 (17) +#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL2 (8) +#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL2 (13) +#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL3 (17) +#define NV_SOR_LANE4_PREEMPHASIS(i) (0x54 + (i)) +#define NV_SOR_POSTCURSOR(i) (0x56 + (i)) +#define NV_SOR_DP_CONFIG(i) (0x58 + (i)) +#define NV_SOR_DP_CONFIG_RD_RESET_VAL_SHIFT (31) +#define NV_SOR_DP_CONFIG_RD_RESET_VAL_POSITIVE (0 << 31) +#define NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE (1 << 31) +#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT (28) +#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE (0 << 28) +#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE (1 << 28) +#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_SHIFT (26) +#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_DISABLE (0 << 26) +#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE (1 << 26) +#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_SHIFT (24) +#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24) +#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24) +#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT (16) +#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK (0xf << 16) +#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT (8) +#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK (0x7f << 8) +#define NV_SOR_DP_CONFIG_WATERMARK_SHIFT (0) +#define NV_SOR_DP_CONFIG_WATERMARK_MASK (0x3f) +#define NV_SOR_DP_MN(i) (0x5a + i) +#define NV_SOR_DP_MN_M_MOD_SHIFT (30) +#define NV_SOR_DP_MN_M_MOD_DEFAULT_MASK (0x3 << 30) +#define NV_SOR_DP_MN_M_MOD_NONE (0 << 30) +#define NV_SOR_DP_MN_M_MOD_INC (1 << 30) +#define NV_SOR_DP_MN_M_MOD_DEC (2 << 30) +#define NV_SOR_DP_MN_M_DELTA_SHIFT (24) +#define NV_SOR_DP_MN_M_DELTA_DEFAULT_MASK (0xf << 24) +#define NV_SOR_DP_MN_N_VAL_SHIFT (0) +#define NV_SOR_DP_MN_N_VAL_DEFAULT_MASK (0xffffff) +#define NV_SOR_DP_PADCTL(i) (0x5c + (i)) +#define NV_SOR_DP_PADCTL_SPARE_SHIFT (25) +#define NV_SOR_DP_PADCTL_SPARE_DEFAULT_MASK (0x7f << 25) +#define NV_SOR_DP_PADCTL_VCO_2X_SHIFT (24) +#define NV_SOR_DP_PADCTL_VCO_2X_DISABLE (0 << 24) +#define NV_SOR_DP_PADCTL_VCO_2X_ENABLE (1 << 24) +#define NV_SOR_DP_PADCTL_PAD_CAL_PD_SHIFT (23) +#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP (0 << 23) +#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN (1 << 23) +#define NV_SOR_DP_PADCTL_TX_PU_SHIFT (22) +#define NV_SOR_DP_PADCTL_TX_PU_DISABLE (0 << 22) +#define NV_SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22) +#define NV_SOR_DP_PADCTL_TX_PU_MASK (1 << 22) +#define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT (20) +#define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK (0x3 << 20) +#define NV_SOR_DP_PADCTL_VCMMODE_SHIFT (16) +#define NV_SOR_DP_PADCTL_VCMMODE_DEFAULT_MASK (0xf << 16) +#define NV_SOR_DP_PADCTL_VCMMODE_TRISTATE (0 << 16) +#define NV_SOR_DP_PADCTL_VCMMODE_TEST_MUX (1 << 16) +#define NV_SOR_DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16) +#define NV_SOR_DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16) +#define NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT (8) +#define NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK (0xff << 8) +#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT (7) +#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7) +#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE (1 << 7) +#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT (6) +#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6) +#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE (1 << 6) +#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT (5) +#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5) +#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE (1 << 5) +#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT (4) +#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4) +#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE (1 << 4) +#define NV_SOR_DP_PADCTL_PD_TXD_3_SHIFT (3) +#define NV_SOR_DP_PADCTL_PD_TXD_3_YES (0 << 3) +#define NV_SOR_DP_PADCTL_PD_TXD_3_NO (1 << 3) +#define NV_SOR_DP_PADCTL_PD_TXD_0_SHIFT (2) +#define NV_SOR_DP_PADCTL_PD_TXD_0_YES (0 << 2) +#define NV_SOR_DP_PADCTL_PD_TXD_0_NO (1 << 2) +#define NV_SOR_DP_PADCTL_PD_TXD_1_SHIFT (1) +#define NV_SOR_DP_PADCTL_PD_TXD_1_YES (0 << 1) +#define NV_SOR_DP_PADCTL_PD_TXD_1_NO (1 << 1) +#define NV_SOR_DP_PADCTL_PD_TXD_2_SHIFT (0) +#define NV_SOR_DP_PADCTL_PD_TXD_2_YES (0) +#define NV_SOR_DP_PADCTL_PD_TXD_2_NO (1) +#define NV_SOR_DP_DEBUG(i) (0x5e + i) +#define NV_SOR_DP_SPARE(i) (0x60 + (i)) +#define NV_SOR_DP_SPARE_REG_SHIFT (3) +#define NV_SOR_DP_SPARE_REG_DEFAULT_MASK (0x1fffffff << 3) +#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SHIFT (2) +#define NV_SOR_DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK (0x1 << 2) +#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK (0 << 2) +#define NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK (1 << 2) +#define NV_SOR_DP_SPARE_PANEL_SHIFT (1) +#define NV_SOR_DP_SPARE_PANEL_EXTERNAL (0 << 1) +#define NV_SOR_DP_SPARE_PANEL_INTERNAL (1 << 1) +#define NV_SOR_DP_SPARE_SEQ_ENABLE_SHIFT (0) +#define NV_SOR_DP_SPARE_SEQ_ENABLE_NO (0) +#define NV_SOR_DP_SPARE_SEQ_ENABLE_YES (1) +#define NV_SOR_DP_AUDIO_CTRL (0x62) +#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS (0x63) +#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK (0x1ffff) +#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT (0) +#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS (0x64) +#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1ffff) +#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_SHIFT (0) +#define NV_SOR_DP_GENERIC_INFOFRAME_HEADER (0x65) +#define NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(i) (0x66 + (i)) +#define NV_SOR_DP_TPG (0x6d) +#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_SHIFT (30) +#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_DISABLE (0 << 30) +#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_ENABLE (1 << 30) +#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_SHIFT (28) +#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS (1 << 28) +#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 28) +#define NV_SOR_DP_TPG_LANE3_PATTERN_SHIFT (24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_DEFAULT_MASK (0xf << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_NOPATTERN (0 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING1 (1 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING2 (2 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING3 (3 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_D102 (4 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_SBLERRRATE (5 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_PRBS7 (6 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_CSTM (7 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE (8 << 24) +#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_SHIFT (22) +#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_DISABLE (0 << 22) +#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_ENABLE (1 << 22) +#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_SHIFT (20) +#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK (0x3 << 20) +#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DISABLE (0 << 20) +#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS (1 << 20) +#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 20) +#define NV_SOR_DP_TPG_LANE2_PATTERN_SHIFT (16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_DEFAULT_MASK (0xf << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_NOPATTERN (0 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING1 (1 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING2 (2 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING3 (3 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_D102 (4 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_SBLERRRATE (5 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_PRBS7 (6 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_CSTM (7 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE (8 << 16) +#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_SHIFT (14) +#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_DISABLE (0 << 14) +#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_ENABLE (1 << 14) +#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_SHIFT (12) +#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK (0x3 << 12) +#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DISABLE (0 << 12) +#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS (1 << 12) +#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12) +#define NV_SOR_DP_TPG_LANE1_PATTERN_SHIFT (8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_DEFAULT_MASK (0xf << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_NOPATTERN (0 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING1 (1 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING2 (2 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING3 (3 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_D102 (4 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_SBLERRRATE (5 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_PRBS7 (6 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_CSTM (7 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE (8 << 8) +#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_SHIFT (6) +#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_DISABLE (0 << 6) +#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_ENABLE (1 << 6) +#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_SHIFT (4) +#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK (0x3 << 4) +#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DISABLE (0 << 4) +#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS (1 << 4) +#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 4) +#define NV_SOR_DP_TPG_LANE0_PATTERN_SHIFT (0) +#define NV_SOR_DP_TPG_LANE0_PATTERN_DEFAULT_MASK (0xf) +#define NV_SOR_DP_TPG_LANE0_PATTERN_NOPATTERN (0) +#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING1 (1) +#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING2 (2) +#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING3 (3) +#define NV_SOR_DP_TPG_LANE0_PATTERN_D102 (4) +#define NV_SOR_DP_TPG_LANE0_PATTERN_SBLERRRATE (5) +#define NV_SOR_DP_TPG_LANE0_PATTERN_PRBS7 (6) +#define NV_SOR_DP_TPG_LANE0_PATTERN_CSTM (7) +#define NV_SOR_DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE (8) + +enum { + training_pattern_disabled = 0, + training_pattern_1 = 1, + training_pattern_2 = 2, + training_pattern_3 = 3, + training_pattern_none = 0xff +}; + +enum tegra_dc_sor_protocol { + SOR_DP, + SOR_LVDS, +}; + +#define SOR_LINK_SPEED_G1_62 6 +#define SOR_LINK_SPEED_G2_7 10 +#define SOR_LINK_SPEED_G5_4 20 +#define SOR_LINK_SPEED_LVDS 7 + +/* todo: combine this and the intel_dp struct into one struct. */ +struct tegra_dc_dp_link_config { + int is_valid; + + /* Supported configuration */ + u8 max_link_bw; + u8 max_lane_count; + int downspread; + int support_enhanced_framing; + u32 bits_per_pixel; + int alt_scramber_reset_cap; /* true for eDP */ + int only_enhanced_framing; /* enhanced_frame_en ignored */ + + /* Actual configuration */ + u8 link_bw; + u8 lane_count; + int enhanced_framing; + int scramble_ena; + + u32 activepolarity; + u32 active_count; + u32 tu_size; + u32 active_frac; + u32 watermark; + + s32 hblank_sym; + s32 vblank_sym; + + /* Training data */ + u32 drive_current; + u32 preemphasis; + u32 postcursor; + u8 aux_rd_interval; + u8 tps3_supported; +}; + +/* TODO: just pull these up into one struct? Need to see how this impacts + * having two channels. + */ +struct tegra_dc_sor_data { + struct tegra_dc *dc; + void *base; + void *pmc_base; + u8 portnum; /* 0 or 1 */ + struct tegra_dc_dp_link_config *link_cfg; + int power_is_up; +}; + +#define TEGRA_SOR_TIMEOUT_MS 1000 +#define TEGRA_SOR_ATTACH_TIMEOUT_MS 1000 +#define TEGRA_DC_POLL_TIMEOUT_MS 50 + +#define CHECK_RET(x) \ + do { \ + ret = (x); \ + if (ret != 0) \ + return ret; \ + } while (0) + +void tegra_dc_sor_enable_dp(struct tegra_dc_sor_data *sor); +int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd); +void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena, + u8 training_pattern, const struct tegra_dc_dp_link_config *link_cfg); +void tegra_dc_sor_set_link_bandwidth(struct tegra_dc_sor_data *sor, u8 link_bw); +void tegra_dc_sor_set_lane_count(struct tegra_dc_sor_data *sor, u8 lane_count); +void tegra_dc_sor_set_panel_power(struct tegra_dc_sor_data *sor, + int power_up); +void tegra_dc_sor_set_internal_panel(struct tegra_dc_sor_data *sor, int is_int); +void tegra_dc_sor_read_link_config(struct tegra_dc_sor_data *sor, u8 *link_bw, + u8 *lane_count); +void tegra_dc_sor_attach(struct tegra_dc_sor_data *sor); +void tegra_dc_sor_set_lane_parm(struct tegra_dc_sor_data *sor, + const struct tegra_dc_dp_link_config *link_cfg); +void tegra_dc_sor_power_down_unused_lanes(struct tegra_dc_sor_data *sor); +void tegra_dc_sor_set_voltage_swing(struct tegra_dc_sor_data *sor); +void tegra_sor_precharge_lanes(struct tegra_dc_sor_data *sor); +void tegra_dp_disable_tx_pu(struct tegra_dc_sor_data *sor); +void tegra_dp_set_pe_vs_pc(struct tegra_dc_sor_data *sor, u32 mask, + u32 pe_reg, u32 vs_reg, u32 pc_reg, u8 pc_supported); +void tegra_dc_detach(struct tegra_dc_sor_data *sor); +#endif /*__TEGRA210_SOR_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/spi.h b/src/soc/nvidia/tegra210/include/soc/spi.h new file mode 100644 index 0000000000..b76622a848 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/spi.h @@ -0,0 +1,67 @@ +/* + * Copyright 2014 Google Inc. + * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __NVIDIA_TEGRA210_SPI_H__ +#define __NVIDIA_TEGRA210_SPI_H__ + +#include <soc/dma.h> +#include <spi-generic.h> +#include <stddef.h> + +struct tegra_spi_regs { + u32 command1; /* 0x000: SPI_COMMAND1 */ + u32 command2; /* 0x004: SPI_COMMAND2 */ + u32 timing1; /* 0x008: SPI_CS_TIM1 */ + u32 timing2; /* 0x00c: SPI_CS_TIM2 */ + u32 trans_status; /* 0x010: SPI_TRANS_STATUS */ + u32 fifo_status; /* 0x014: SPI_FIFO_STATUS */ + u32 tx_data; /* 0x018: SPI_TX_DATA */ + u32 rx_data; /* 0x01c: SPI_RX_DATA */ + u32 dma_ctl; /* 0x020: SPI_DMA_CTL */ + u32 dma_blk; /* 0x024: SPI_DMA_BLK */ + u32 rsvd[56]; /* 0x028-0x107: reserved */ + u32 tx_fifo; /* 0x108: SPI_FIFO1 */ + u32 rsvd2[31]; /* 0x10c-0x187 reserved */ + u32 rx_fifo; /* 0x188: SPI_FIFO2 */ + u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */ +} __attribute__((packed)); +check_member(tegra_spi_regs, spare_ctl, 0x18c); + +enum spi_xfer_mode { + XFER_MODE_NONE = 0, + XFER_MODE_PIO, + XFER_MODE_DMA, +}; + +struct tegra_spi_channel { + struct tegra_spi_regs *regs; + + /* static configuration */ + struct spi_slave slave; + unsigned int req_sel; + + int dual_mode; /* for x2 transfers with bit interleaving */ + + /* context (used internally) */ + u8 *in_buf, *out_buf; + struct apb_dma_channel *dma_out, *dma_in; + enum spi_xfer_mode xfer_mode; +}; + +struct tegra_spi_channel *tegra_spi_init(unsigned int bus); + +#endif /* __NVIDIA_TEGRA210_SPI_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/sysctr.h b/src/soc/nvidia/tegra210/include/soc/sysctr.h new file mode 100644 index 0000000000..e5a894c389 --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/sysctr.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_SYSCTR_H__ +#define __SOC_NVIDIA_TEGRA210_SYSCTR_H__ + +#include <stdint.h> + +enum { + SYSCTR_CNTCR_EN = 1 << 0, + SYSCTR_CNTCR_HDBG = 1 << 1, + SYSCTR_CNTCR_FCREQ = 1 << 8 +}; + +struct sysctr_regs { + uint32_t cntcr; + uint32_t cntsr; + uint32_t cntcv0; + uint32_t cntcv1; + uint8_t _rsv0[0x10]; + uint32_t cntfid0; + uint32_t cntfid1; + uint8_t _rsv1[0xfa8]; + uint32_t counterid4; + uint32_t counterid5; + uint32_t counterid6; + uint32_t counterid7; + uint32_t counterid0; + uint32_t counterid1; + uint32_t counterid2; + uint32_t counterid3; + uint32_t counterid8; + uint32_t counterid9; + uint32_t counterid10; + uint32_t counterid11; +}; +check_member(sysctr_regs, counterid11, 0xffc); + +#endif /* __SOC_NVIDIA_TEGRA210_SYSCTR_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h new file mode 100644 index 0000000000..058e26faca --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/tegra_dsi.h @@ -0,0 +1,223 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#ifndef __TEGRA_DSI_H__ +#define __TEGRA_DSI_H__ + +#define DSI_INCR_SYNCPT 0x00 +#define DSI_INCR_SYNCPT_CONTROL 0x01 +#define DSI_INCR_SYNCPT_ERROR 0x02 +#define DSI_CTXSW 0x08 +#define DSI_RD_DATA 0x09 +#define DSI_WR_DATA 0x0a +#define DSI_POWER_CONTROL 0x0b +#define DSI_POWER_CONTROL_ENABLE (1 << 0) +#define DSI_INT_ENABLE 0x0c +#define DSI_INT_STATUS 0x0d +#define DSI_INT_MASK 0x0e +#define DSI_HOST_CONTROL 0x0f +#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21) +#define DSI_HOST_CONTROL_CRC_RESET (1 << 20) +#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12) +#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12) +#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12) +#define DSI_HOST_CONTROL_RAW (1 << 6) +#define DSI_HOST_CONTROL_HS (1 << 5) +#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4) +#define DSI_HOST_CONTROL_IMM_BTA (1 << 3) +#define DSI_HOST_CONTROL_PKT_BTA (1 << 2) +#define DSI_HOST_CONTROL_CS (1 << 1) +#define DSI_HOST_CONTROL_ECC (1 << 0) +#define DSI_CONTROL 0x10 +#define DSI_CONTROL_HS_CLK_CTRL (1 << 20) +#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16) +#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12) +#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8) +#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4) +#define DSI_CONTROL_DCS_ENABLE (1 << 3) +#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2) +#define DSI_CONTROL_VIDEO_ENABLE (1 << 1) +#define DSI_CONTROL_HOST_ENABLE (1 << 0) +#define DSI_SOL_DELAY 0x11 +#define DSI_MAX_THRESHOLD 0x12 +#define DSI_TRIGGER 0x13 +#define DSI_TRIGGER_HOST (1 << 1) +#define DSI_TRIGGER_VIDEO (1 << 0) +#define DSI_TX_CRC 0x14 +#define DSI_STATUS 0x15 +#define DSI_STATUS_IDLE (1 << 10) +#define DSI_STATUS_UNDERFLOW (1 << 9) +#define DSI_STATUS_OVERFLOW (1 << 8) +#define DSI_INIT_SEQ_CONTROL 0x1a +#define DSI_INIT_SEQ_DATA_0 0x1b +#define DSI_INIT_SEQ_DATA_1 0x1c +#define DSI_INIT_SEQ_DATA_2 0x1d +#define DSI_INIT_SEQ_DATA_3 0x1e +#define DSI_INIT_SEQ_DATA_4 0x1f +#define DSI_INIT_SEQ_DATA_5 0x20 +#define DSI_INIT_SEQ_DATA_6 0x21 +#define DSI_INIT_SEQ_DATA_7 0x22 +#define DSI_PKT_SEQ_0_LO 0x23 +#define DSI_PKT_SEQ_0_HI 0x24 +#define DSI_PKT_SEQ_1_LO 0x25 +#define DSI_PKT_SEQ_1_HI 0x26 +#define DSI_PKT_SEQ_2_LO 0x27 +#define DSI_PKT_SEQ_2_HI 0x28 +#define DSI_PKT_SEQ_3_LO 0x29 +#define DSI_PKT_SEQ_3_HI 0x2a +#define DSI_PKT_SEQ_4_LO 0x2b +#define DSI_PKT_SEQ_4_HI 0x2c +#define DSI_PKT_SEQ_5_LO 0x2d +#define DSI_PKT_SEQ_5_HI 0x2e +#define DSI_DCS_CMDS 0x33 +#define DSI_PKT_LEN_0_1 0x34 +#define DSI_PKT_LEN_2_3 0x35 +#define DSI_PKT_LEN_4_5 0x36 +#define DSI_PKT_LEN_6_7 0x37 +#define DSI_PHY_TIMING_0 0x3c +#define DSI_PHY_TIMING_1 0x3d +#define DSI_PHY_TIMING_2 0x3e +#define DSI_BTA_TIMING 0x3f + +#define DSI_TIMING_FIELD(value, period, hwinc) \ + ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff) + +#define DSI_TIMEOUT_0 0x44 +#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16) +#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0) +#define DSI_TIMEOUT_1 0x45 +#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16) +#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0) +#define DSI_TO_TALLY 0x46 +#define DSI_TALLY_TA(x) (((x) & 0xff) << 16) +#define DSI_TALLY_LRX(x) (((x) & 0xff) << 8) +#define DSI_TALLY_HTX(x) (((x) & 0xff) << 0) +#define DSI_PAD_CONTROL_0 0x4b +#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) +#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) +#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) +#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24) +#define DSI_PAD_CONTROL_CD 0x4c +#define DSI_PAD_CD_STATUS 0x4d +#define DSI_VIDEO_MODE_CONTROL 0x4e +#define DSI_PAD_CONTROL_1 0x4f +#define DSI_PAD_CONTROL_2 0x50 +#define DSI_PAD_OUT_CLK(x) (((x) & 0x7) << 0) +#define DSI_PAD_LP_DN(x) (((x) & 0x7) << 4) +#define DSI_PAD_LP_UP(x) (((x) & 0x7) << 8) +#define DSI_PAD_SLEW_DN(x) (((x) & 0x7) << 12) +#define DSI_PAD_SLEW_UP(x) (((x) & 0x7) << 16) +#define DSI_PAD_CONTROL_3 0x51 +#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12) +#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8) +#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4) +#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) +#define DSI_PAD_CONTROL_4 0x52 +#define DSI_GANGED_MODE_CONTROL 0x53 +#define DSI_GANGED_MODE_CONTROL_ENABLE (1 << 0) +#define DSI_GANGED_MODE_START 0x54 +#define DSI_GANGED_MODE_SIZE 0x55 +#define DSI_RAW_DATA_BYTE_COUNT 0x56 +#define DSI_ULTRA_LOW_POWER_CONTROL 0x57 +#define DSI_INIT_SEQ_DATA_8 0x58 +#define DSI_INIT_SEQ_DATA_9 0x59 +#define DSI_INIT_SEQ_DATA_10 0x5a +#define DSI_INIT_SEQ_DATA_11 0x5b +#define DSI_INIT_SEQ_DATA_12 0x5c +#define DSI_INIT_SEQ_DATA_13 0x5d +#define DSI_INIT_SEQ_DATA_14 0x5e +#define DSI_INIT_SEQ_DATA_15 0x5f + +#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) +#define PKT_LEN0(len) (((len) & 0x07) << 0) +#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) +#define PKT_LEN1(len) (((len) & 0x07) << 10) +#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) +#define PKT_LEN2(len) (((len) & 0x07) << 20) + +#define PKT_LP (1 << 30) +#define NUM_PKT_SEQ 12 + +#define APB_MISC_GP_MIPI_PAD_CTRL_0 (TEGRA_APB_MISC_GP_BASE + 0x20) +#define DSIB_MODE_SHIFT 1 +#define DSIB_MODE_CSI (0 << DSIB_MODE_SHIFT) +#define DSIB_MODE_DSI (1 << DSIB_MODE_SHIFT) + +/* + * pixel format as used in the DSI_CONTROL_FORMAT field + */ +enum tegra_dsi_format { + TEGRA_DSI_FORMAT_16P, + TEGRA_DSI_FORMAT_18NP, + TEGRA_DSI_FORMAT_18P, + TEGRA_DSI_FORMAT_24P, +}; + +enum dsi_dev { + DSI_A = 0, + DSI_B, + NUM_DSI, +}; + +struct panel_jdi; +struct tegra_mipi_device; +struct mipi_dsi_host; +struct mipi_dsi_msg; + +#define MAX_DSI_VIDEO_FIFO_DEPTH 96 +#define MAX_DSI_HOST_FIFO_DEPTH 64 + +struct tegra_dsi { + struct panel_jdi *panel; + //struct tegra_output output; + void *regs; + u8 channel; + unsigned long clk_rate; + + unsigned long flags; + enum mipi_dsi_pixel_format format; + unsigned int lanes; + + struct tegra_mipi_device *mipi; + struct mipi_dsi_host host; + bool enabled; + + unsigned int video_fifo_depth; + unsigned int host_fifo_depth; + + /* for ganged-mode support */ + unsigned int ganged_lanes; + struct tegra_dsi *slave; + int ganged_mode; + + struct tegra_dsi *master; +}; + +static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi, + unsigned long reg) +{ + return read32(dsi->regs + (reg << 2)); +} + +static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value, + unsigned long reg) +{ + write32(dsi->regs + (reg << 2), value); +} + +#endif /* __TEGRA_DSI_H__ */ diff --git a/src/soc/nvidia/tegra210/include/soc/verstage.h b/src/soc/nvidia/tegra210/include/soc/verstage.h new file mode 100644 index 0000000000..6c37218e9e --- /dev/null +++ b/src/soc/nvidia/tegra210/include/soc/verstage.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ +#define __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ + +void verstage_mainboard_init(void); + +#endif /* __SOC_NVIDIA_TEGRA210_SOC_VERSTAGE_H__ */ |