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| author | Furquan Shaikh <furquan@google.com> | 2015-10-15 15:50:30 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2015-11-07 03:29:35 +0100 |
| commit | fdb3a8d07d46c0011555029e041890dc668ec7f0 (patch) | |
| tree | 18594c3e21c1d153865360d09f727a0cad63e82e /src/soc/nvidia/tegra210/ramstage.c | |
| parent | b3f6ad35221984419ee0998f47b778d669d1636e (diff) | |
| download | coreboot-fdb3a8d07d46c0011555029e041890dc668ec7f0.tar.xz | |
arm64: Remove cpu intialization through device-tree
Since, SMP support is removed for ARM64, there is no need for CPU
initialization to be performed via device-tree.
Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/11913
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/ramstage.c')
| -rw-r--r-- | src/soc/nvidia/tegra210/ramstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index f55c256a25..5c375106a2 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -19,6 +19,7 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/mmu_operations.h> +#include <soc/mtc.h> void arm64_arch_timer_init(void) { @@ -54,4 +55,9 @@ void arm64_soc_init(void) trustzone_region_init(); tegra210_mmu_init(); + + clock_init_arm_generic_timer(); + + if (tegra210_run_mtc() != 0) + printk(BIOS_ERR, "MTC: No training data.\n"); } |