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authorTom Warren <twarren@nvidia.com>2015-08-04 13:08:50 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-08-28 06:40:43 +0000
commit50967870a9b0a55a5c973785803d7fe8921c1107 (patch)
tree18c9e0a8ebc961bafeffa20bfe64567d9b83e76d /src/soc/nvidia/tegra210/soc.c
parent8b3851969d6546ae920f52eb681631cd9b9aff46 (diff)
downloadcoreboot-50967870a9b0a55a5c973785803d7fe8921c1107.tar.xz
T210: Add 128MB VPR allocation/carveout
The NV security team requested that coreboot allocate a 128MB region in SDRAM for VPR (Video Protection Region). We had previously just disabled the VPR by setting BOM/SIZE to 0. Once allocated, the VPR will be locked from further access. The ALLOW_TZ_WRITE_ACCESS bit is _not_ set, as dynamic VPR config is not supported at this time (i.e. trusted code can _not_ remap or resize the VPR). BUG=None BRANCH=None TEST=Built and booted on my P5 A44. Saw the VPR region in the boot spew (ID:3 [f6800000 - fe800000]). Dumped the MC VideoProtect registers and verified their values. Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a7481dba31dc39f482f8a7bfdaba1d1f4fc3cb81 Original-Change-Id: Ia19af485430bc09dbba28fcef5de16de851f81aa Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290475 Original-Reviewed-by: Hyung Taek Ryoo <hryoo@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Hridya Valsaraju <hvalsaraju@nvidia.com> Original-(cherry picked from commit 9629b318eb17b145315531509f950da02483114f) Original-Reviewed-on: https://chromium-review.googlesource.com/291095 Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Change-Id: I19a93c915990644177c491c8212f2cf356d4d17d Reviewed-on: http://review.coreboot.org/11384 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/soc.c')
-rw-r--r--src/soc/nvidia/tegra210/soc.c20
1 files changed, 0 insertions, 20 deletions
diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c
index 829acb2d73..9e67531b76 100644
--- a/src/soc/nvidia/tegra210/soc.c
+++ b/src/soc/nvidia/tegra210/soc.c
@@ -82,23 +82,6 @@ static struct cpu_control_ops cntrl_ops = {
};
-static void lock_down_vpr(void)
-{
- struct tegra_mc_regs *regs = (void *)(uintptr_t)TEGRA_MC_BASE;
-
- write32(&regs->video_protect_bom, 0);
- write32(&regs->video_protect_size_mb, 0);
-
- write32(&regs->video_protect_gpu_override_0, 1);
- /*
- * Set both _ACCESS bits so that kernel/secure code
- * can reconfig VPR careveout as needed from the TrustZone.
- */
-
- write32(&regs->video_protect_reg_ctrl,
- (MC_VPR_WR_ACCESS_DISABLE | MC_VPR_ALLOW_TZ_WR_ACCESS_ENABLE));
-}
-
static void soc_init(device_t dev)
{
struct soc_nvidia_tegra210_config *cfg;
@@ -109,9 +92,6 @@ static void soc_init(device_t dev)
spintable_init((void *)cfg->spintable_addr);
arch_initialize_cpus(dev, &cntrl_ops);
- /* Lock down VPR */
- lock_down_vpr();
-
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
if (vboot_skip_display_init())
printk(BIOS_INFO, "Skipping display init.\n");