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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-08-05 16:18:56 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-09 01:26:18 +0000 |
| commit | 98f43a1f757a89afa4e48d15ff48abdd7e62f46b (patch) | |
| tree | ccc883a4cd689ff6ddac0c69650e56eb0dc227d3 /src/soc/nvidia/tegra210/spi.c | |
| parent | 08eca5dcc3659e5211eec94ef4c3c3fc4bf5d90b (diff) | |
| download | coreboot-98f43a1f757a89afa4e48d15ff48abdd7e62f46b.tar.xz | |
cpu/x86 mp_init: Add option for AMD INIT SIPI sequence
The common code adheres to the Intel requirement of bringing up the
cores with INIT SIPI SIPI. This sequence is tolerated on some AMD
AMD CPUs but fails on others. Add a way to skip the second SIPI.
TEST=Mock up on grunt and verify no errors
BUG=b:138919564
Change-Id: I201869003ddc7d04d332cd5734ac6d63979d89e0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34759
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/spi.c')
0 files changed, 0 insertions, 0 deletions