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| author | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-11-10 00:35:02 +0100 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2019-03-07 12:47:01 +0000 |
| commit | c9b7d1fb57787d7037a5bce031a1300d13f5df40 (patch) | |
| tree | 57788b70b069229693dae5727cb8acc54eee3c14 /src/soc/nvidia/tegra210 | |
| parent | 7a732b4781e7b83abda3230055d7110e1db730f3 (diff) | |
| download | coreboot-c9b7d1fb57787d7037a5bce031a1300d13f5df40.tar.xz | |
security/tpm: Fix TCPA log feature
Until now the TCPA log wasn't working correctly.
* Refactor TCPA log code.
* Add TCPA log dump fucntion.
* Make TCPA log available in bootblock.
* Fix TCPA log formatting.
* Add x86 and Cavium memory for early log.
Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/nvidia/tegra210')
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/memlayout.ld | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index d807c06599..18171354d5 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -28,18 +28,19 @@ SECTIONS { SRAM_START(0x40000000) - PRERAM_CBMEM_CONSOLE(0x40000000, 4K) - PRERAM_CBFS_CACHE(0x40001000, 36K) - VBOOT2_WORK(0x4000A000, 12K) + PRERAM_CBMEM_CONSOLE(0x40000000, 2K) + PRERAM_CBFS_CACHE(0x40000800, 32K) + VBOOT2_WORK(0x40008800, 12K) + VBOOT2_TPM_LOG(0x4000B800, 2K) #if ENV_ARM64 - STACK(0x4000D000, 3K) + STACK(0x4000C000, 3K) #else /* AVP gets a separate stack to avoid any chance of handoff races. */ - STACK(0x4000DC00, 3K) + STACK(0x4000CC00, 3K) #endif - TIMESTAMP(0x4000E800, 2K) - BOOTBLOCK(0x4000F000, 28K) - VERSTAGE(0x40016000, 64K) - ROMSTAGE(0x40026000, 104K) + TIMESTAMP(0x4000D800, 2K) + BOOTBLOCK(0x4000E000, 28K) + VERSTAGE(0x40015000, 66K) + ROMSTAGE(0x40025800, 106K) SRAM_END(0x40040000) DRAM_START(0x80000000) |