diff options
| author | Julius Werner <jwerner@chromium.org> | 2014-04-11 18:23:12 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-12-16 23:29:16 +0100 |
| commit | e57c30315309a82de64da21dd83bba79864033c9 (patch) | |
| tree | 1d312f055a981d5a9c5e077b2a783e5525b0cfda /src/soc/nvidia/tegra | |
| parent | d712ec47d48f765dbc9008d94b58842d6c24b544 (diff) | |
| download | coreboot-e57c30315309a82de64da21dd83bba79864033c9.tar.xz | |
tegra124: clock: Enforce PLL constraints for VCO and CF
This patch adds some documentation to the additional PLL divisor
constraints on the intermediary VCO and CF values that we just found out
about. PLLC divisors for some oscillators had to be adjusted
accordingly.
It also adds a new clock_get_pll_input_khz() function to replace
clock_get_osc_khz() in cases where you want to factor in the built-in
predivider for 38.4 and 48 MHz oscillators.
BUG=None
TEST=Still boots.
Original-Change-Id: Ib6e026dbab9fcc50d6d81a884774ad07c7b0dbc3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/194474
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 3f1f565baf100edcd486055e4317c675c882396f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I091f42bf952a4b58ef2c30586baa5bf7496fa599
Reviewed-on: http://review.coreboot.org/7768
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/nvidia/tegra')
| -rw-r--r-- | src/soc/nvidia/tegra/usb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index 39477e17d3..e0455ed05c 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -28,7 +28,7 @@ void usb_setup_utmip(struct usb_ctlr *usb) { /* KHz formulas were guessed from U-Boot constants. Formats unclear. */ - int khz = clock_get_osc_khz(); + int khz = clock_get_pll_input_khz(); /* Stop UTMI+ crystal clock while we mess with its settings */ clrbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ |