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authorJulius Werner <jwerner@chromium.org>2015-02-19 14:51:15 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:22:28 +0200
commit2f37bd65518865688b9234afce0d467508d6f465 (patch)
treeeba5ed799de966299602b30c70d51dd40eaadd73 /src/soc/nvidia/tegra
parent1f60f971fc89ef841e81b978964b38278d597b1d (diff)
downloadcoreboot-2f37bd65518865688b9234afce0d467508d6f465.tar.xz
arm(64): Globally replace writel(v, a) with write32(a, v)
This patch is a raw application of the following spatch to src/: @@ expression A, V; @@ - writel(V, A) + write32(A, V) @@ expression A, V; @@ - writew(V, A) + write16(A, V) @@ expression A, V; @@ - writeb(V, A) + write8(A, V) @@ expression A; @@ - readl(A) + read32(A) @@ expression A; @@ - readb(A) + read8(A) BRANCH=none BUG=chromium:444723 TEST=None (depends on next patch) Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6 Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/254864 Reviewed-on: http://review.coreboot.org/9836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra')
-rw-r--r--src/soc/nvidia/tegra/apbmisc.c4
-rw-r--r--src/soc/nvidia/tegra/gpio.c4
-rw-r--r--src/soc/nvidia/tegra/i2c.c12
-rw-r--r--src/soc/nvidia/tegra/pingroup.c2
-rw-r--r--src/soc/nvidia/tegra/pinmux.c2
-rw-r--r--src/soc/nvidia/tegra/usb.c30
6 files changed, 27 insertions, 27 deletions
diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c
index 292d21d02f..3f7df5bd0e 100644
--- a/src/soc/nvidia/tegra/apbmisc.c
+++ b/src/soc/nvidia/tegra/apbmisc.c
@@ -26,12 +26,12 @@ static struct apbmisc *misc = (struct apbmisc *)TEGRA_APB_MISC_BASE;
void enable_jtag(void)
{
- writel(PP_CONFIG_CTL_JTAG, &misc->pp_config_ctl);
+ write32(&misc->pp_config_ctl, PP_CONFIG_CTL_JTAG);
}
void clamp_tristate_inputs(void)
{
- writel(PP_PINMUX_CLAMP_INPUTS, &misc->pp_pinmux_global);
+ write32(&misc->pp_pinmux_global, PP_PINMUX_CLAMP_INPUTS);
}
void tegra_revision_info(struct tegra_revision *id)
diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c
index 8179580add..e0561c057d 100644
--- a/src/soc/nvidia/tegra/gpio.c
+++ b/src/soc/nvidia/tegra/gpio.c
@@ -67,8 +67,8 @@ static void gpio_write_port(int index, size_t offset, u32 mask, u32 value)
u32 new_reg = (reg & ~mask) | (value & mask);
if (new_reg != reg) {
- writel(new_reg,
- (u8 *)&gpio_banks[bank] + offset + port * sizeof(u32));
+ write32((u8 *)&gpio_banks[bank] + offset + port * sizeof(u32),
+ new_reg);
}
}
diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c
index b9a5f42a37..1d5df3c342 100644
--- a/src/soc/nvidia/tegra/i2c.c
+++ b/src/soc/nvidia/tegra/i2c.c
@@ -40,9 +40,9 @@ static void do_bus_clear(int bus)
// 4. Set TERMINATE condition (1 = IMMEDIATE)
bc = read32(&regs->bus_clear_config);
bc |= I2C_BUS_CLEAR_CONFIG_BC_TERMINATE_IMMEDIATE;
- writel(bc, &regs->bus_clear_config);
+ write32(&regs->bus_clear_config, bc);
// 4.1 Set MSTR_CONFIG_LOAD and wait for clear
- writel(I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE, &regs->config_load);
+ write32(&regs->config_load, I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE);
for (i = 0; i < timeout_ms * 10 && (read32(&regs->config_load) &
I2C_CONFIG_LOAD_MSTR_CONFIG_LOAD_ENABLE); i++) {
printk(BIOS_DEBUG, "%s: wait for MSTR_CONFIG_LOAD to clear\n",
@@ -50,7 +50,7 @@ static void do_bus_clear(int bus)
udelay(100);
}
// 5. Set ENABLE to start the bus clear op
- writel(bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE, &regs->bus_clear_config);
+ write32(&regs->bus_clear_config, bc | I2C_BUS_CLEAR_CONFIG_BC_ENABLE);
for (i = 0; i < timeout_ms * 10 && (read32(&regs->bus_clear_config) &
I2C_BUS_CLEAR_CONFIG_BC_ENABLE); i++) {
printk(BIOS_DEBUG, "%s: wait for bus clear completion\n",
@@ -74,7 +74,7 @@ static int tegra_i2c_send_recv(int bus, int read,
rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT;
while (header_words && tx_empty) {
- writel(*headers++, &regs->tx_packet_fifo);
+ write32(&regs->tx_packet_fifo, *headers++);
header_words--;
tx_empty--;
}
@@ -96,7 +96,7 @@ static int tegra_i2c_send_recv(int bus, int read,
int todo = MIN(data_len, sizeof(word));
memcpy(&word, data, todo);
- writel(word, &regs->tx_packet_fifo);
+ write32(&regs->tx_packet_fifo, word);
data_len -= todo;
data += sizeof(word);
tx_empty--;
@@ -208,5 +208,5 @@ void i2c_init(unsigned bus)
{
struct tegra_i2c_regs * const regs = tegra_i2c_info[bus].base;
- writel(I2C_CNFG_PACKET_MODE_EN, &regs->cnfg);
+ write32(&regs->cnfg, I2C_CNFG_PACKET_MODE_EN);
}
diff --git a/src/soc/nvidia/tegra/pingroup.c b/src/soc/nvidia/tegra/pingroup.c
index c856c173ac..332e05aeaa 100644
--- a/src/soc/nvidia/tegra/pingroup.c
+++ b/src/soc/nvidia/tegra/pingroup.c
@@ -26,7 +26,7 @@ static uint32_t *pingroup_regs = (void *)TEGRA_APB_PINGROUP_BASE;
void pingroup_set_config(int group_index, uint32_t config)
{
- writel(config, &pingroup_regs[group_index]);
+ write32(&pingroup_regs[group_index], config);
}
uint32_t pingroup_get_config(int group_index)
diff --git a/src/soc/nvidia/tegra/pinmux.c b/src/soc/nvidia/tegra/pinmux.c
index a88a063cac..f28b0266e7 100644
--- a/src/soc/nvidia/tegra/pinmux.c
+++ b/src/soc/nvidia/tegra/pinmux.c
@@ -26,7 +26,7 @@ static uint32_t *pinmux_regs = (void *)TEGRA_APB_PINMUX_BASE;
void pinmux_set_config(int pin_index, uint32_t config)
{
- writel(config, &pinmux_regs[pin_index]);
+ write32(&pinmux_regs[pin_index], config);
}
uint32_t pinmux_get_config(int pin_index)
diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c
index c666c40f3b..4a069fa02e 100644
--- a/src/soc/nvidia/tegra/usb.c
+++ b/src/soc/nvidia/tegra/usb.c
@@ -126,7 +126,7 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t
{
int timeout = 1000;
- writel(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */
+ write32(&usb->ehci_usbcmd, 1 << 1); /* Host Controller Reset */
/* TODO: Resets are long, find way to parallelize... or just use XHCI */
while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1))
/* wait for HC to reset */;
@@ -137,11 +137,11 @@ static void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type t
}
/* Controller mode: HOST */
- writel(3 << 0, &usb->usb_mode);
+ write32(&usb->usb_mode, 3 << 0);
/* Parallel transceiver selct */
- writel(type << 29, &usb->lpm_ctrl);
+ write32(&usb->lpm_ctrl, type << 29);
/* Tx FIFO Burst thresh */
- writel(0x10 << 16, &usb->tx_fill_tuning);
+ write32(&usb->tx_fill_tuning, 0x10 << 16);
}
/* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */
@@ -157,27 +157,27 @@ void usb_setup_utmip(void *usb_base)
udelay(1);
/* Take stuff out of pwrdn and add some magic numbers from U-Boot */
- writel(0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0,
- &usb->utmip.xcvr0);
- writel(0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0, &usb->utmip.xcvr1);
- writel(1 << 19 | 1 << 16 | 1 << 9 | 0, &usb->utmip.tx);
- writel(0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0,
- &usb->utmip.hsrx0);
+ write32(&usb->utmip.xcvr0,
+ 0x8 << 25 | 0x3 << 22 | 0 << 21 | 0 << 18 | 0 << 16 | 0 << 14 | 1 << 13 | 0x1 << 10 | 0x1 << 8 | 0x4 << 0 | 0);
+ write32(&usb->utmip.xcvr1, 0x7 << 18 | 0 << 4 | 0 << 2 | 0 << 0 | 0);
+ write32(&usb->utmip.tx, 1 << 19 | 1 << 16 | 1 << 9 | 0);
+ write32(&usb->utmip.hsrx0,
+ 0x2 << 30 | 1 << 28 | 0x1 << 24 | 0x3 << 21 | 0x11 << 15 | 0x10 << 10 | 0);
/* U-Boot claims the USBD values for these are used across all UTMI+
* PHYs. That sounds so horribly wrong that I'm not going to implement
* it, but keep it in mind if we're ever not using the USBD port. */
- writel(0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0,
- &usb->utmip.bias0);
+ write32(&usb->utmip.bias0,
+ 0x1 << 24 | 1 << 23 | 1 << 22 | 1 << 11 | 0 << 10 | 0x1 << 2 | 0x2 << 0 | 0);
- writel(khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0, &usb->utmip.bias1);
+ write32(&usb->utmip.bias1, khz / 2200 << 3 | 1 << 2 | 0 << 0 | 0);
- writel(0xffff << 16 | 25 * khz / 10 << 0 | 0, &usb->utmip.debounce);
+ write32(&usb->utmip.debounce, 0xffff << 16 | 25 * khz / 10 << 0 | 0);
udelay(1);
setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */
- writel(1 << 12 | 0 << 11 | 0, &usb->suspend_ctrl);
+ write32(&usb->suspend_ctrl, 1 << 12 | 0 << 11 | 0);
usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP);
printk(BIOS_DEBUG, "USB controller @ %p set up with UTMI+ PHY\n",usb_base);