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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-07-11 14:31:34 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-12 17:09:21 +0000 |
| commit | 56352e1f8055c3495c71e1856f0d26923be44ed0 (patch) | |
| tree | 89c017af6cf28989a4d4c9fd40fd53e6ea5a22cf /src/soc/nvidia | |
| parent | b14f3b8b0b005a5de8f5bcbb84d44fce9d0bc6b8 (diff) | |
| download | coreboot-56352e1f8055c3495c71e1856f0d26923be44ed0.tar.xz | |
mb/siemens/mc_apl3: Enable LPSS UART 1
By setting the GPIOs 42 and 43 to native function 1 the LPSS UART 1 is
activated.
Change-Id: I74abd1b6fb5459cf11a5bdee182c99462f613b7a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/nvidia')
0 files changed, 0 insertions, 0 deletions