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authorTom Warren <twarren@nvidia.com>2014-11-13 13:16:28 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-10 12:02:34 +0200
commit8315622ff1bd898d839144abf0310524a35f8e1a (patch)
treed201d047a7f34aee9d8e6421c1197c8500dfef5f /src/soc/nvidia
parent9f7d3ad1369d7964d7e1afb11ac6229ba57ab386 (diff)
downloadcoreboot-8315622ff1bd898d839144abf0310524a35f8e1a.tar.xz
google/rush: Add I2C1 init and audio clock enable/resets
This should allow the max98090 codec to play beeps via AHUB/I2S1 thru the depthcharge sound driver. BUG=none BRANCH=none TEST=Saw max98090 codec init signon and register dump. No sound yet. Change-Id: I1ee0b61f5cbfe587ebd16b7dd9dce08d9d62c2c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4ee2ce3704711a9e00531b7599a1bcf194203ec Original-Change-Id: I0bc8401e76b2c80a01083ac933a39f6cd4d1b78a Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229496 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Mike Frysinger <vapier@chromium.org> Reviewed-on: http://review.coreboot.org/9429 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia')
-rw-r--r--src/soc/nvidia/tegra132/include/soc/clock.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h
index f0d05e1750..e62e0aad32 100644
--- a/src/soc/nvidia/tegra132/include/soc/clock.h
+++ b/src/soc/nvidia/tegra132/include/soc/clock.h
@@ -187,6 +187,9 @@ enum {
PLLE = 7,
PLLA = 8,
UNUSED = 100,
+ UNUSED1 = 101,
+ UNUSED2 = 102,
+ UNUSED3 = 103,
};
#define CLK_SRC_DEV_ID(dev, src) CLK_SRC_##dev##_##src
@@ -221,6 +224,8 @@ enum {
CLK_SRC_DEVICE(SDMMC3, PLLP, PLLC2, PLLC, PLLC3, PLLM, PLLE, CLK_M),
CLK_SRC_DEVICE(SDMMC4, PLLP, PLLC2, PLLC, PLLC3, PLLM, PLLE, CLK_M),
CLK_SRC_DEVICE(UARTA, PLLP, PLLC2, PLLC, PLLC3, PLLM, UNUSED, CLK_M),
+ CLK_SRC_DEVICE(i2s1, PLLA, UNUSED, CLK_S, UNUSED1, PLLP, UNUSED2, CLK_M),
+ CLK_SRC_DEVICE(extperiph1, PLLA, CLK_S, PLLP, CLK_M, PLLE, UNUSED, UNUSED1),
};
/* PLL stabilization delay in usec */