diff options
| author | Jimmy Zhang <jimmzhang@nvidia.com> | 2015-01-06 11:49:34 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-14 09:04:17 +0200 |
| commit | fb391fa24c33b29ac0fde386133ca168a527eefe (patch) | |
| tree | 1e3af146dc74ec4b3aed0927c1f8132b5c07457d /src/soc/nvidia | |
| parent | a43db197f3bc8c19aa99276dbcd5b260ebc41803 (diff) | |
| download | coreboot-fb391fa24c33b29ac0fde386133ca168a527eefe.tar.xz | |
rush: Add dp related parameters
Add these parameters so that they can be specified in devicetree.
BUG=chrome-os-partner:34336
BRANCH=none
TEST=build ryu and rush
Change-Id: I77ee16263e1ce6a8c32b3cd203c1b8a499514a8e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c3b254936e696f81ca7eeeb7f6968a5350352b59
Original-Change-Id: Iba47afe95c3889047a82582730be7a253fae76e7
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/238940
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9611
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra132/chip.h | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h index fbbef500d4..a083676eec 100644 --- a/src/soc/nvidia/tegra132/chip.h +++ b/src/soc/nvidia/tegra132/chip.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2014 Google Inc. + * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -69,7 +69,31 @@ struct soc_nvidia_tegra132_config { int refresh; /* display refresh rate */ int pixel_clock; /* dc pixel clock source rate */ + + u32 panel_bits_per_pixel; + + /* dp specific fields */ + struct { + /* pwm to use to set display contrast */ + int pwm; + + /* HPD related timing */ + int vdd_to_hpd_delay_ms; + int hpd_unplug_min_us; + int hpd_plug_min_us; + int hpd_irq_min_us; + + /* The minimum link configuraton settings */ + u32 lane_count; + u32 enhanced_framing; + u32 link_bw; + u32 drive_current; + u32 preemphasis; + u32 postcursor; + } dp; + int win_opt; + void *dc_data; }; #endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */ |