t132: Add shared romstage

There's no reason to duplicate code in the mainboards. Therefore,
drive the flow of romstage boot in the SoC. This allows for
easier scaling with multiple devices.

BUG=None
BRANCH=None
TEST=Built and booted to same place as before.

Original-Change-Id: I0d4df84034b19353daad0da1f722b820596c4f55
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205992
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit de4310af6f6dbeedd7432683d1d1fe12ce48f46e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie74f0eb1c983aff92d3cbafb7fe7d9d7cb65ae19
Reviewed-on: http://review.coreboot.org/8575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

3 files changed, 74 insertions, 0 deletions

diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 855ef24832..a98467431b 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -24,6 +24,7 @@ romstage-y += spi.c
 romstage-y += i2c.c
 romstage-y += dma.c
 romstage-y += monotonic_timer.c
+romstage-y += romstage.c
 romstage-y += sdram.c
 romstage-y += sdram_lp0.c
 romstage-y += ../tegra/gpio.c
diff --git a/src/soc/nvidia/tegra132/include/soc/sdram_configs.h b/src/soc/nvidia/tegra132/include/soc/sdram_configs.h
new file mode 100644
index 0000000000..300be1093c
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/sdram_configs.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__
+#define __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__
+
+#include <soc/nvidia/tegra132/sdram.h>
+
+/* Loads SDRAM configurations for current system. */
+const struct sdram_params *get_sdram_config(void);
+
+#endif  /* __SOC_NVIDIA_TEGRA132_SDRAM_CONFIGS_H__ */
diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c
new file mode 100644
index 0000000000..a4a0636cab
--- /dev/null
+++ b/src/soc/nvidia/tegra132/romstage.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/stages.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <arch/exception.h>
+
+#include <soc/sdram_configs.h>
+#include <soc/nvidia/tegra132/sdram.h>
+
+void main(void)
+{
+	void *entry;
+
+	console_init();
+	exception_init();
+
+	printk(BIOS_INFO, "T132: romstage here\n");
+
+	sdram_init(get_sdram_config());
+
+	printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
+
+	while (1);
+
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
+	stage_exit(entry);
+}