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| author | Duncan Laurie <dlaurie@chromium.org> | 2014-09-08 20:47:52 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-27 06:37:18 +0100 |
| commit | 9ecafd967c4232b9b38dda9ce663bb33777a2828 (patch) | |
| tree | 973e02db823963d72b680422b51ab779154d379a /src/soc/nvidia | |
| parent | 46134728402601abc85a6a9ee01d37f0d50cc705 (diff) | |
| download | coreboot-9ecafd967c4232b9b38dda9ce663bb33777a2828.tar.xz | |
samus: Update SPD with correct geometry and timings
This memory is also x16 and needs slight tweak to tRFCmin
in order to be functional.
BUG=chrome-os-partner:31833
BRANCH=None
TEST=build and boot on EVT unit with this config
Original-Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217190
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 6c4bf71c8c8e1e46ce290441c2e21bc7b2839760)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I389936d85e61a0a939cd4485fcc0723d2a0aa4d6
Reviewed-on: http://review.coreboot.org/8972
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/nvidia')
0 files changed, 0 insertions, 0 deletions