diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-05-13 12:19:15 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-05-14 21:26:54 +0000 |
| commit | bcac1cbacd2613e02c865182f445a02e6cdf45e7 (patch) | |
| tree | 5f9da3c751043da426a6a4b8b3bed33eac7dbbc6 /src/soc/nvidia | |
| parent | 1dac6058723efa8b2a1ea3bfff8443e39e10fdf2 (diff) | |
| download | coreboot-bcac1cbacd2613e02c865182f445a02e6cdf45e7.tar.xz | |
soc/nvidia/tegra124: add resources during read_resources()
The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources in
read_resources().
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I16f0439679471366723a0084918a20cd95834831
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41372
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra124/soc.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index ffc8771d7d..00c7009e9a 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -14,7 +14,7 @@ * Will break if we get 2. Sigh. * We assume it's all multiples of MiB for MMUs sake. */ -static void soc_enable(struct device *dev) +static void soc_read_resources(struct device *dev) { u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; @@ -41,9 +41,8 @@ static void soc_init(struct device *dev) } static struct device_operations soc_ops = { - .read_resources = noop_read_resources, + .read_resources = soc_read_resources, .set_resources = noop_set_resources, - .enable_resources = soc_enable, .init = soc_init, }; |