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authorJoseph Lo <josephl@nvidia.com>2015-10-28 15:34:22 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-11-05 17:40:11 +0100
commita28e9084bf58dc4094a3383b2887a50b9756f2e1 (patch)
tree2c1ad30439cd26648b36c42f6cb504dbfebdd63c /src/soc/nvidia
parent2524be4aff63e01637d28d6866fa23a513a3b8b1 (diff)
downloadcoreboot-a28e9084bf58dc4094a3383b2887a50b9756f2e1.tar.xz
nvidia/tegra210: lp0_resume: clear the MC_INTSTATUS if MC_INTMASK was 0
The MC/SMMU should be resumed by the kernel. And the unexpected value in the MC_INTSTATUS should be cleared before that. Or it will cause some noisy MC interrupt once we enable the IRQ in the kernel. BUG=chrome-os-partner:46796 BRANCH=none TEST=LP0 suspend/resume test and the EMEM decode/arbitration errors should not be observed on resume. Change-Id: I5b32fa58ebcb8e7db6ffc88e13cca050753f621a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 07cb719caf40b59c5519fcf212c2fb50f006812e Original-Change-Id: I4d34905c04effd54d0d0edf8809e192283db2ca3 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309248 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Original-Commit-Queue: Joseph Lo <yushun.lo@gmail.com> Original-Tested-by: Joseph Lo <yushun.lo@gmail.com> Original-(cherry picked from commit 13cbcaf441bd762af9cf00eff24eb7709db38d95) Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309497 Original-Commit-Ready: Andrew Bresticker <abrestic@chromium.org> Reviewed-on: http://review.coreboot.org/12321 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia')
-rw-r--r--src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
index 000d48db4c..15477d6fe2 100644
--- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c
@@ -335,6 +335,8 @@ enum {
static uint32_t *pmc_set_sw_clamp_ptr = (void *)(PMC_CTLR_BASE + 0x47c);
/* Memory controller registers. */
+static uint32_t *mc_intstatus_ptr = (void *)(MC_CTLR_BASE);
+static uint32_t *mc_intmask_ptr = (void *)(MC_CTLR_BASE + 0x4);
static uint32_t *mc_video_protect_size_mb_ptr = (void *)(MC_CTLR_BASE + 0x64c);
static uint32_t *mc_video_protect_reg_ctrl_ptr =
@@ -979,6 +981,13 @@ void lp0_resume(void)
write32(pmc_dpd_sample_ptr, 0);
udelay(10);
+ /* Clear the MC_INTSTATUS if MC_INTMASK was 0. */
+ if (!read32(mc_intmask_ptr)) {
+ uint32_t mc_intst_val = read32(mc_intstatus_ptr);
+ if (mc_intst_val)
+ write32(mc_intstatus_ptr, mc_intst_val);
+ }
+
/*
* Set both _ACCESS bits so that kernel/secure code
* can reconfig VPR careveout as needed from the TrustZone.