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authorJulius Werner <jwerner@chromium.org>2019-03-05 16:53:33 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-08 08:33:24 +0000
commitcd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch)
tree8e89136e2da7cf54453ba8c112eda94415b56242 /src/soc/nvidia
parentb3a8cc54dbaf833c590a56f912209a5632b71f49 (diff)
downloadcoreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/nvidia')
-rw-r--r--src/soc/nvidia/tegra210/ccplex.c2
-rw-r--r--src/soc/nvidia/tegra210/include/soc/console_uart.h10
-rw-r--r--src/soc/nvidia/tegra210/include/soc/mtc.h2
-rw-r--r--src/soc/nvidia/tegra210/romstage.c2
-rw-r--r--src/soc/nvidia/tegra210/soc.c2
5 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/nvidia/tegra210/ccplex.c b/src/soc/nvidia/tegra210/ccplex.c
index cc1e284b66..ce46e5ee35 100644
--- a/src/soc/nvidia/tegra210/ccplex.c
+++ b/src/soc/nvidia/tegra210/ccplex.c
@@ -43,7 +43,7 @@ static void enable_cpu_power_partitions(void)
power_ungate_partition(POWER_PARTID_C0NC);
power_ungate_partition(POWER_PARTID_CE0);
- if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) {
+ if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) {
/*
* Deassert reset signal of all the secondary CPUs.
* PMC and flow controller will take over the power sequence
diff --git a/src/soc/nvidia/tegra210/include/soc/console_uart.h b/src/soc/nvidia/tegra210/include/soc/console_uart.h
index fc30481326..e35b582fa2 100644
--- a/src/soc/nvidia/tegra210/include/soc/console_uart.h
+++ b/src/soc/nvidia/tegra210/include/soc/console_uart.h
@@ -29,19 +29,19 @@ enum console_uart_id {
static inline enum console_uart_id console_uart_get_id(void)
{
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTA))
+ if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTA))
return UART_ID_A;
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTB))
+ if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTB))
return UART_ID_B;
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTC))
+ if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTC))
return UART_ID_C;
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTD))
+ if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTD))
return UART_ID_D;
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTE))
+ if (CONFIG(CONSOLE_SERIAL_TEGRA210_UARTE))
return UART_ID_E;
return UART_ID_NONE;
diff --git a/src/soc/nvidia/tegra210/include/soc/mtc.h b/src/soc/nvidia/tegra210/include/soc/mtc.h
index ca369ad3cf..df13cc4f77 100644
--- a/src/soc/nvidia/tegra210/include/soc/mtc.h
+++ b/src/soc/nvidia/tegra210/include/soc/mtc.h
@@ -18,7 +18,7 @@
#include <boot/coreboot_tables.h>
-#if IS_ENABLED(CONFIG_HAVE_MTC)
+#if CONFIG(HAVE_MTC)
int tegra210_run_mtc(void);
void soc_add_mtc(struct lb_header *header);
diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c
index 213d69d6ba..bfa3c0afb4 100644
--- a/src/soc/nvidia/tegra210/romstage.c
+++ b/src/soc/nvidia/tegra210/romstage.c
@@ -43,7 +43,7 @@ void romstage(void)
printk(BIOS_INFO, "T210: romstage here\n");
-#if IS_ENABLED(CONFIG_BOOTROM_SDRAM_INIT)
+#if CONFIG(BOOTROM_SDRAM_INIT)
printk(BIOS_INFO, "T210 romstage: SDRAM init done by BootROM, RAMCODE = %d\n",
sdram_get_ram_code());
#else
diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c
index b8359987f9..a9d6835b3a 100644
--- a/src/soc/nvidia/tegra210/soc.c
+++ b/src/soc/nvidia/tegra210/soc.c
@@ -78,7 +78,7 @@ static void enable_tegra210_dev(struct device *dev)
if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &soc_ops;
- if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
+ if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT))
return;
if (display_init_required())