diff options
| author | Tom Warren <twarren@nvidia.com> | 2014-07-16 09:03:45 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-13 00:04:03 +0100 |
| commit | 31818c98afae06ba77df383bfa013f9ede16430d (patch) | |
| tree | c24c1dbd7a093bd3d22063f0dcd0f71926f8a3bb /src/soc/nvidia | |
| parent | 01dde90eb9c070018fc11b007159c8d130b2809d (diff) | |
| download | coreboot-31818c98afae06ba77df383bfa013f9ede16430d.tar.xz | |
ryu: Add support for full LPDDR3 SDRAM BCT init via BootROM
Once LPDDR3 init is supported in the ryu romstage, this can
be reverted. Note that this 528MHz BCT has been pre-qualed
by NVIDIA AE's, but will be updated as more tuning is done.
BUG=none
BRANCH=none
TEST=Builds, BCT is in binary, but I have no HW here to test on
Original-Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208384
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 660e40cb473d47ce763e79d6061367bf381a1c48)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I29ad31fc83f45ca8f92809a7dc252cf984c8c6fe
Reviewed-on: http://review.coreboot.org/8643
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra132/Kconfig | 6 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/romstage.c | 6 |
2 files changed, 11 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 8a5d087a7f..0ce29a03fa 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -99,4 +99,10 @@ config TRUSTZONE_CARVEOUT_SIZE_MB help Size of Trust Zone area in MiB to reserve in memory map. +config BOOTROM_SDRAM_INIT + bool "SoC BootROM does SDRAM init with full BCT" + default n + help + Use during Ryu LPDDR3 bringup + endif diff --git a/src/soc/nvidia/tegra132/romstage.c b/src/soc/nvidia/tegra132/romstage.c index e7e545d002..2a1bd46d07 100644 --- a/src/soc/nvidia/tegra132/romstage.c +++ b/src/soc/nvidia/tegra132/romstage.c @@ -38,9 +38,13 @@ void romstage(void) printk(BIOS_INFO, "T132: romstage here\n"); +#if CONFIG_BOOTROM_SDRAM_INIT + printk(BIOS_INFO, "T132 romstage: SDRAM init done by BootROM, RAMCODE = %d\n", + sdram_get_ram_code()); +#else sdram_init(get_sdram_config()); printk(BIOS_INFO, "T132 romstage: sdram_init done\n"); - +#endif cbmem_initialize(); ccplex_cpu_prepare(); |