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| author | Andre Heider <a.heider@gmail.com> | 2018-02-15 18:15:17 +0100 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2018-02-20 20:39:33 +0000 |
| commit | feefcca601ce54450fc849d337b82193566ce272 (patch) | |
| tree | bfaa1fc5c7e9134b4de50a71db7fe598e957613a /src/soc/nvidia | |
| parent | 92712d361d0ecdd33d5fb097630b0b61e96ab5bd (diff) | |
| download | coreboot-feefcca601ce54450fc849d337b82193566ce272.tar.xz | |
soc/nvidia/tegra210: add missing bl31 params to ATF config
The ATF tegra210 platform supports more than the currently used
'tzdram_size' parameter, see plat/nvidia/tegra/include/tegra_private.h
in the ATF tree.
Add the missing parameters and set them accordingly. The passed UART id
is based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx, so ATF now uses the
same port for console output as coreboot.
Successfully tested with UARTB.
Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/nvidia')
| -rw-r--r-- | src/soc/nvidia/tegra210/arm_tf.c | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c index 28966c8baa..3ffcb0e0aa 100644 --- a/src/soc/nvidia/tegra210/arm_tf.c +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -17,12 +17,18 @@ #include <arm_tf.h> #include <assert.h> #include <soc/addressmap.h> +#include <soc/console_uart.h> #include <stdlib.h> #include <string.h> #include <symbols.h> typedef struct bl31_plat_params { - uint32_t tzdram_size; + /* TZ memory size */ + uint64_t tzdram_size; + /* TZ memory base */ + uint64_t tzdram_base; + /* UART port ID */ + int uart_id; } bl31_plat_params_t; static bl31_plat_params_t t210_plat_params; @@ -31,11 +37,35 @@ void *soc_get_bl31_plat_params(bl31_params_t *params) { uintptr_t tz_base_mib; size_t tz_size_mib; + int uart_id = 0; carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib); assert(tz_size_mib < 4096); + + switch (console_uart_get_id()) { + case UART_ID_NONE: + break; + case UART_ID_A: + uart_id = 1; + break; + case UART_ID_B: + uart_id = 2; + break; + case UART_ID_C: + uart_id = 3; + break; + case UART_ID_D: + uart_id = 4; + break; + case UART_ID_E: + uart_id = 5; + break; + } + t210_plat_params.tzdram_size = tz_size_mib * MiB; + t210_plat_params.tzdram_base = tz_base_mib * MiB; + t210_plat_params.uart_id = uart_id; dcache_clean_by_mva(&t210_plat_params, sizeof(t210_plat_params)); |